Phallaka Kik

Array ( [id] => 13417365 [patent_doc_number] => 20180260225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => COMPUTER SYSTEM PERFORMANCE ANALYZER [patent_app_type] => utility [patent_app_number] => 15/977075 [patent_app_country] => US [patent_app_date] => 2018-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7218 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15977075 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13396119 [patent_doc_number] => 20180249602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-30 [patent_title] => SYSTEMS AND METHODS FOR FLUX CANCELATION IN ELECTRONIC DEVICES [patent_app_type] => utility [patent_app_number] => 15/965766 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15965766 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13524715 [patent_doc_number] => 20180313900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => BATTERY SYSTEM AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/951617 [patent_app_country] => US [patent_app_date] => 2018-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15951617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15701581 [patent_doc_number] => 10606970 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Selection of corners and/or margins using statistical static timing analysis of an integrated circuit [patent_app_type] => utility [patent_app_number] => 15/951713 [patent_app_country] => US [patent_app_date] => 2018-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5123 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15951713 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13580375 [patent_doc_number] => 20180341736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => SEMICONDUCTOR DEVICE, CORRESPONDING MASK AND METHOD FOR GENERATING LAYOUT OF SAME [patent_app_type] => utility [patent_app_number] => 15/949804 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15124429 [patent_doc_number] => 20190348848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => Modular Charging and System Wall-Mounted Charging Device and Modular Power Devices [patent_app_type] => utility [patent_app_number] => 15/950081 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9408 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15950081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16849369 [patent_doc_number] => 20210150114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => SIMULATION APPARATUS, SIMULATION METHOD, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 16/622048 [patent_app_country] => US [patent_app_date] => 2018-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16795 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16622048 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16763930 [patent_doc_number] => 20210109511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM [patent_app_type] => utility [patent_app_number] => 16/496604 [patent_app_country] => US [patent_app_date] => 2018-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16496604 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15181533 [patent_doc_number] => 20190361358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => COMPUTATIONAL METROLOGY [patent_app_type] => utility [patent_app_number] => 16/481143 [patent_app_country] => US [patent_app_date] => 2018-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 37170 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16481143 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15426327 [patent_doc_number] => 10546093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Computer-implemented method and computing system for designing integrated circuit by considering process variations of wire [patent_app_type] => utility [patent_app_number] => 15/867470 [patent_app_country] => US [patent_app_date] => 2018-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 10446 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15867470 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15981451 [patent_doc_number] => 10671052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Synchronized parallel tile computation for large area lithography simulation [patent_app_type] => utility [patent_app_number] => 15/867437 [patent_app_country] => US [patent_app_date] => 2018-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 13665 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15867437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15473369 [patent_doc_number] => 10552563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Digital design with bundled data asynchronous logic and body-biasing tuning [patent_app_type] => utility [patent_app_number] => 15/866876 [patent_app_country] => US [patent_app_date] => 2018-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6640 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15866876 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14705117 [patent_doc_number] => 10380308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Power distribution networks (PDNs) using hybrid grid and pillar arrangements [patent_app_type] => utility [patent_app_number] => 15/867022 [patent_app_country] => US [patent_app_date] => 2018-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7333 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15867022 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14669869 [patent_doc_number] => 10372836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Integrated circuit buffering solutions considering sink delays [patent_app_type] => utility [patent_app_number] => 15/848053 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7675 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15848053 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13974391 [patent_doc_number] => 10216552 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => Robust and adaptable management of event counters [patent_app_type] => utility [patent_app_number] => 15/821131 [patent_app_country] => US [patent_app_date] => 2017-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5028 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15821131 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12241253 [patent_doc_number] => 20180074116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'Critical Path Architect' [patent_app_type] => utility [patent_app_number] => 15/817643 [patent_app_country] => US [patent_app_date] => 2017-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8811 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15817643 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12583719 [patent_doc_number] => 20180086402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => MOBILE POWER SUPPLY TRAILER APPARATUS [patent_app_type] => utility [patent_app_number] => 15/809455 [patent_app_country] => US [patent_app_date] => 2017-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 415 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15809455 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14062389 [patent_doc_number] => 10235489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-19 [patent_title] => Method for optimizing the design of micro-fluidic devices [patent_app_type] => utility [patent_app_number] => 15/800508 [patent_app_country] => US [patent_app_date] => 2017-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 33 [patent_no_of_words] => 15842 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15800508 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14229195 [patent_doc_number] => 20190126770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => BATTERY STATE ESTIMATION CONTROL LOGIC AND ARCHITECTURES FOR ELECTRIC STORAGE SYSTEMS [patent_app_type] => utility [patent_app_number] => 15/794049 [patent_app_country] => US [patent_app_date] => 2017-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8430 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15794049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14239499 [patent_doc_number] => 20190131922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => POWER SUPPLY APPARATUS EMPLOYING SOLAR PANELS [patent_app_type] => utility [patent_app_number] => 15/794108 [patent_app_country] => US [patent_app_date] => 2017-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1615 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15794108 [rel_patent_id] =>[rel_patent_doc_number] =>)