Search

Phallaka Kik

Examiner (ID: 11978, Phone: (571)272-1895 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2764, 2768, 2763, 2851, 2304
Total Applications
1951
Issued Applications
1745
Pending Applications
98
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14705077 [patent_doc_number] => 10380288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Structure and generation method of clock distribution network [patent_app_type] => utility [patent_app_number] => 15/659577 [patent_app_country] => US [patent_app_date] => 2017-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2694 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15659577 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/659577
Structure and generation method of clock distribution network Jul 24, 2017 Issued
Array ( [id] => 14395813 [patent_doc_number] => 10311190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Virtual hierarchical layer patterning [patent_app_type] => utility [patent_app_number] => 15/654511 [patent_app_country] => US [patent_app_date] => 2017-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10881 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15654511 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/654511
Virtual hierarchical layer patterning Jul 18, 2017 Issued
Array ( [id] => 14365061 [patent_doc_number] => 10303837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Virtual cell model geometry compression [patent_app_type] => utility [patent_app_number] => 15/654565 [patent_app_country] => US [patent_app_date] => 2017-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11302 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15654565 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/654565
Virtual cell model geometry compression Jul 18, 2017 Issued
Array ( [id] => 12571881 [patent_doc_number] => 10019548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-10 [patent_title] => Method of generating modified layout and system therefor [patent_app_type] => utility [patent_app_number] => 15/651616 [patent_app_country] => US [patent_app_date] => 2017-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 8778 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15651616 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/651616
Method of generating modified layout and system therefor Jul 16, 2017 Issued
Array ( [id] => 14299329 [patent_doc_number] => 10289792 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-14 [patent_title] => Systems and methods for clustering pins for power [patent_app_type] => utility [patent_app_number] => 15/636410 [patent_app_country] => US [patent_app_date] => 2017-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15636410 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/636410
Systems and methods for clustering pins for power Jun 27, 2017 Issued
Array ( [id] => 14427751 [patent_doc_number] => 10318681 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-11 [patent_title] => Static leakage current and power estimation [patent_app_type] => utility [patent_app_number] => 15/635461 [patent_app_country] => US [patent_app_date] => 2017-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 8738 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15635461 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/635461
Static leakage current and power estimation Jun 27, 2017 Issued
Array ( [id] => 14299317 [patent_doc_number] => 10289786 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-14 [patent_title] => Circuit design transformation for automatic latency reduction [patent_app_type] => utility [patent_app_number] => 15/634016 [patent_app_country] => US [patent_app_date] => 2017-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 9065 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15634016 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/634016
Circuit design transformation for automatic latency reduction Jun 26, 2017 Issued
Array ( [id] => 12121289 [patent_doc_number] => 20180004876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'Reset Domain Crossing Management Using Unified Power Format' [patent_app_type] => utility [patent_app_number] => 15/633542 [patent_app_country] => US [patent_app_date] => 2017-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15633542 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/633542
Reset domain crossing management using unified power format Jun 25, 2017 Issued
Array ( [id] => 14887409 [patent_doc_number] => 10423748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-24 [patent_title] => Systems and methods for obfuscating a circuit design [patent_app_type] => utility [patent_app_number] => 15/633412 [patent_app_country] => US [patent_app_date] => 2017-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 78 [patent_figures_cnt] => 81 [patent_no_of_words] => 67058 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15633412 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/633412
Systems and methods for obfuscating a circuit design Jun 25, 2017 Issued
Array ( [id] => 12128372 [patent_doc_number] => 20180011958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-11 [patent_title] => 'METHODS FOR ENGINEERING INTEGRATED CIRCUIT DESIGN AND DEVELOPMENT' [patent_app_type] => utility [patent_app_number] => 15/633186 [patent_app_country] => US [patent_app_date] => 2017-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 56879 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15633186 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/633186
Methods for engineering integrated circuit design and development Jun 25, 2017 Issued
Array ( [id] => 12128363 [patent_doc_number] => 20180011948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-11 [patent_title] => 'SYSTEMS FOR ENGINEERING INTEGRATED CIRCUIT DESIGN AND DEVELOPMENT' [patent_app_type] => utility [patent_app_number] => 15/633253 [patent_app_country] => US [patent_app_date] => 2017-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 56246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15633253 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/633253
Systems for engineering integrated circuit design and development Jun 25, 2017 Issued
Array ( [id] => 14299327 [patent_doc_number] => 10289791 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-14 [patent_title] => Anchor-point based hierarchical electronic design process [patent_app_type] => utility [patent_app_number] => 15/631569 [patent_app_country] => US [patent_app_date] => 2017-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6434 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15631569 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/631569
Anchor-point based hierarchical electronic design process Jun 22, 2017 Issued
Array ( [id] => 14008473 [patent_doc_number] => 10222690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Method of optimizing a mask using pixel-based learning and method for manufacturing a semiconductor device using an optimized mask [patent_app_type] => utility [patent_app_number] => 15/631763 [patent_app_country] => US [patent_app_date] => 2017-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8123 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15631763 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/631763
Method of optimizing a mask using pixel-based learning and method for manufacturing a semiconductor device using an optimized mask Jun 22, 2017 Issued
Array ( [id] => 14549445 [patent_doc_number] => 10343161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Customizable microfluidic device with programmable microfluidic nodes [patent_app_type] => utility [patent_app_number] => 15/630980 [patent_app_country] => US [patent_app_date] => 2017-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 13238 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15630980 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/630980
Customizable microfluidic device with programmable microfluidic nodes Jun 22, 2017 Issued
Array ( [id] => 13724119 [patent_doc_number] => 20170373015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME AND GENERATION METHOD OF UNIQUE INFORMATION [patent_app_type] => utility [patent_app_number] => 15/631889 [patent_app_country] => US [patent_app_date] => 2017-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5175 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15631889 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/631889
Semiconductor device, method of manufacturing the same and generation method of unique information Jun 22, 2017 Issued
Array ( [id] => 12121276 [patent_doc_number] => 20180004862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'Optimizing The Ordering Of The Inputs To Large Commutative-Associative Trees Of Logic Gates' [patent_app_type] => utility [patent_app_number] => 15/630885 [patent_app_country] => US [patent_app_date] => 2017-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15630885 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/630885
Optimizing the ordering of the inputs to large commutative-associative trees of logic gates Jun 21, 2017 Issued
Array ( [id] => 14490071 [patent_doc_number] => 10331826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => False path timing exception handler circuit [patent_app_type] => utility [patent_app_number] => 15/630394 [patent_app_country] => US [patent_app_date] => 2017-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3947 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15630394 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/630394
False path timing exception handler circuit Jun 21, 2017 Issued
Array ( [id] => 14556193 [patent_doc_number] => 10346558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Integrated circuit buffering solutions considering sink delays [patent_app_type] => utility [patent_app_number] => 15/630343 [patent_app_country] => US [patent_app_date] => 2017-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15630343 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/630343
Integrated circuit buffering solutions considering sink delays Jun 21, 2017 Issued
Array ( [id] => 14588903 [patent_doc_number] => 20190222060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => WIRELESS POWER TRANSMITTER AND RECEIVER [patent_app_type] => utility [patent_app_number] => 16/308202 [patent_app_country] => US [patent_app_date] => 2017-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14630 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16308202 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/308202
WIRELESS POWER TRANSMITTER AND RECEIVER Jun 4, 2017 Abandoned
Array ( [id] => 14718911 [patent_doc_number] => 20190250519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => SUBSTRATE MEASUREMENT RECIPE CONFIGURATION TO IMPROVE DEVICE MATCHING [patent_app_type] => utility [patent_app_number] => 16/305913 [patent_app_country] => US [patent_app_date] => 2017-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16540 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16305913 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/305913
Substrate measurement recipe configuration to improve device matching May 31, 2017 Issued
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