Search

Phallaka Kik

Examiner (ID: 11978, Phone: (571)272-1895 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2764, 2768, 2763, 2851, 2304
Total Applications
1951
Issued Applications
1745
Pending Applications
98
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14123063 [patent_doc_number] => 10248390 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-02 [patent_title] => Resource sharing workflows within executable graphical models [patent_app_type] => utility [patent_app_number] => 14/993773 [patent_app_country] => US [patent_app_date] => 2016-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 17670 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14993773 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/993773
Resource sharing workflows within executable graphical models Jan 11, 2016 Issued
Array ( [id] => 13767515 [patent_doc_number] => 10176100 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-08 [patent_title] => Cache coherency process [patent_app_type] => utility [patent_app_number] => 14/976085 [patent_app_country] => US [patent_app_date] => 2015-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7992 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14976085 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/976085
Cache coherency process Dec 20, 2015 Issued
Array ( [id] => 12407043 [patent_doc_number] => 09969278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-15 [patent_title] => Mechanism for locking and fault detection in the electrical vehicle supply equipment cord reel [patent_app_type] => utility [patent_app_number] => 14/968145 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2738 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14968145 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/968145
Mechanism for locking and fault detection in the electrical vehicle supply equipment cord reel Dec 13, 2015 Issued
Array ( [id] => 10740733 [patent_doc_number] => 20160086884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'MITIGATING ELECTROMIGRATION EFFECTS USING PARALLEL PILLARS' [patent_app_type] => utility [patent_app_number] => 14/958109 [patent_app_country] => US [patent_app_date] => 2015-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6709 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14958109 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/958109
Mitigating electromigration effects using parallel pillars Dec 2, 2015 Issued
Array ( [id] => 11285754 [patent_doc_number] => 09501609 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-22 [patent_title] => 'Selection of corners and/or margins using statistical static timing analysis of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 14/957128 [patent_app_country] => US [patent_app_date] => 2015-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5163 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14957128 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/957128
Selection of corners and/or margins using statistical static timing analysis of an integrated circuit Dec 1, 2015 Issued
Array ( [id] => 14705101 [patent_doc_number] => 10380300 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-13 [patent_title] => Flexible power query interfaces and infrastructures [patent_app_type] => utility [patent_app_number] => 14/951293 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 15525 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14951293 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/951293
Flexible power query interfaces and infrastructures Nov 23, 2015 Issued
Array ( [id] => 12532668 [patent_doc_number] => 10007744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-26 [patent_title] => Process based metrology target design [patent_app_type] => utility [patent_app_number] => 14/941347 [patent_app_country] => US [patent_app_date] => 2015-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 8533 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14941347 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/941347
Process based metrology target design Nov 12, 2015 Issued
Array ( [id] => 12249375 [patent_doc_number] => 09922151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => '3D circuit design method' [patent_app_type] => utility [patent_app_number] => 14/941331 [patent_app_country] => US [patent_app_date] => 2015-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 5833 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14941331 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/941331
3D circuit design method Nov 12, 2015 Issued
Array ( [id] => 11629894 [patent_doc_number] => 20170140083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'Modeling Memory In Emulation Based On Cache' [patent_app_type] => utility [patent_app_number] => 14/941471 [patent_app_country] => US [patent_app_date] => 2015-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4562 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14941471 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/941471
Modeling memory in emulation based on cache Nov 12, 2015 Issued
Array ( [id] => 11630797 [patent_doc_number] => 20170140986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'SELF-ALIGNED METAL CUT AND VIA FOR BACK-END-OF-LINE (BEOL) PROCESSES FOR SEMICONDUCTOR INTEGRATED CIRCUIT (IC) FABRICATION, AND RELATED PROCESSES AND DEVICES' [patent_app_type] => utility [patent_app_number] => 14/939561 [patent_app_country] => US [patent_app_date] => 2015-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 6434 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14939561 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/939561
Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices Nov 11, 2015 Issued
Array ( [id] => 11622153 [patent_doc_number] => 20170132340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'SIMULATION OF MODIFICATIONS TO MICROPROCESSOR DESIGN' [patent_app_type] => utility [patent_app_number] => 14/937903 [patent_app_country] => US [patent_app_date] => 2015-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7972 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14937903 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/937903
Simulation of modifications to microprocessor design Nov 10, 2015 Issued
Array ( [id] => 11902948 [patent_doc_number] => 09772377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'Circuit division method for test pattern generation and circuit division device for test pattern generation' [patent_app_type] => utility [patent_app_number] => 14/938000 [patent_app_country] => US [patent_app_date] => 2015-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 43 [patent_no_of_words] => 20553 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14938000 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/938000
Circuit division method for test pattern generation and circuit division device for test pattern generation Nov 10, 2015 Issued
Array ( [id] => 11890107 [patent_doc_number] => 09760669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Congestion mitigation by wire ordering' [patent_app_type] => utility [patent_app_number] => 14/937995 [patent_app_country] => US [patent_app_date] => 2015-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7788 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14937995 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/937995
Congestion mitigation by wire ordering Nov 10, 2015 Issued
Array ( [id] => 11577891 [patent_doc_number] => 09633155 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-25 [patent_title] => 'Circuit modification' [patent_app_type] => utility [patent_app_number] => 14/936690 [patent_app_country] => US [patent_app_date] => 2015-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5509 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14936690 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/936690
Circuit modification Nov 9, 2015 Issued
Array ( [id] => 12101281 [patent_doc_number] => 09858377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Constraint-driven pin optimization for hierarchical design convergence' [patent_app_type] => utility [patent_app_number] => 14/936920 [patent_app_country] => US [patent_app_date] => 2015-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4207 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14936920 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/936920
Constraint-driven pin optimization for hierarchical design convergence Nov 9, 2015 Issued
Array ( [id] => 11445443 [patent_doc_number] => 20170046464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'SLACK REDISTRIBUTION FOR ADDITIONAL POWER RECOVERY' [patent_app_type] => utility [patent_app_number] => 14/879216 [patent_app_country] => US [patent_app_date] => 2015-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3931 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14879216 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/879216
Slack redistribution for additional power recovery Oct 8, 2015 Issued
Array ( [id] => 13639593 [patent_doc_number] => 09846756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-19 [patent_title] => Layout method for printed circuit board [patent_app_type] => utility [patent_app_number] => 14/843113 [patent_app_country] => US [patent_app_date] => 2015-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3509 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14843113 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/843113
Layout method for printed circuit board Sep 1, 2015 Issued
Array ( [id] => 10494161 [patent_doc_number] => 20150379184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'LAYOUT METHOD FOR PRINTED CIRCUIT BOARD' [patent_app_type] => utility [patent_app_number] => 14/843094 [patent_app_country] => US [patent_app_date] => 2015-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3617 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14843094 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/843094
LAYOUT METHOD FOR PRINTED CIRCUIT BOARD Sep 1, 2015 Abandoned
Array ( [id] => 11366265 [patent_doc_number] => 20170004246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'INTRA-RUN DESIGN DECISION PROCESS FOR CIRCUIT SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 14/837102 [patent_app_country] => US [patent_app_date] => 2015-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3360 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14837102 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/837102
Intra-run design decision process for circuit synthesis Aug 26, 2015 Issued
Array ( [id] => 11474277 [patent_doc_number] => 20170061060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'TIMING CONSTRAINTS FORMULATION FOR HIGHLY REPLICATED DESIGN MODULES' [patent_app_type] => utility [patent_app_number] => 14/837050 [patent_app_country] => US [patent_app_date] => 2015-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3996 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14837050 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/837050
Timing constraints formulation for highly replicated design modules Aug 26, 2015 Issued
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