Search

Phallaka Kik

Examiner (ID: 8609, Phone: (571)272-1895 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2768, 2851, 2763, 2304, 2825, 2764
Total Applications
1982
Issued Applications
1763
Pending Applications
103
Abandoned Applications
144

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18298653 [patent_doc_number] => 20230108339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => Circuit Implementation on Processing Circuitry [patent_app_type] => utility [patent_app_number] => 18/077187 [patent_app_country] => US [patent_app_date] => 2022-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18077187 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/077187
Circuit implementation on processing circuitry Dec 6, 2022 Issued
Array ( [id] => 18668814 [patent_doc_number] => 11775718 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Methods and apparatus to simulate metastability for circuit design verification [patent_app_type] => utility [patent_app_number] => 18/072842 [patent_app_country] => US [patent_app_date] => 2022-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 13993 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18072842 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/072842
Methods and apparatus to simulate metastability for circuit design verification Nov 30, 2022 Issued
Array ( [id] => 18881706 [patent_doc_number] => 20240005075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => GRAPHIC NEURAL NETWORK ACCELERATION SOLUTION WITH CUSTOMIZED BOARD FOR SOLID-STATE DRIVES [patent_app_type] => utility [patent_app_number] => 18/071970 [patent_app_country] => US [patent_app_date] => 2022-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18071970 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/071970
GRAPHIC NEURAL NETWORK ACCELERATION SOLUTION WITH CUSTOMIZED BOARD FOR SOLID-STATE DRIVES Nov 29, 2022 Pending
Array ( [id] => 18711580 [patent_doc_number] => 20230334209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => CIRCUIT VERIFICATION METHOD [patent_app_type] => utility [patent_app_number] => 18/059961 [patent_app_country] => US [patent_app_date] => 2022-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4176 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18059961 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/059961
Circuit verification method Nov 28, 2022 Issued
Array ( [id] => 20388438 [patent_doc_number] => 12488166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Implementing burst transfers for predicated memory accesses in loop bodies for high-level synthesis [patent_app_type] => utility [patent_app_number] => 18/059348 [patent_app_country] => US [patent_app_date] => 2022-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7359 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18059348 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/059348
Implementing burst transfers for predicated memory accesses in loop bodies for high-level synthesis Nov 27, 2022 Issued
Array ( [id] => 19291053 [patent_doc_number] => 12030397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Cord reel variable current thermal management and damage detection [patent_app_type] => utility [patent_app_number] => 17/991967 [patent_app_country] => US [patent_app_date] => 2022-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 2920 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17991967 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/991967
Cord reel variable current thermal management and damage detection Nov 21, 2022 Issued
Array ( [id] => 18788228 [patent_doc_number] => 20230376659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => VLSI PLACEMENT OPTIMIZATION USING SELF-SUPERVISED GRAPH CLUSTERING [patent_app_type] => utility [patent_app_number] => 18/051984 [patent_app_country] => US [patent_app_date] => 2022-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17051 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18051984 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/051984
VLSI placement optimization using self-supervised graph clustering Nov 1, 2022 Issued
Array ( [id] => 18471678 [patent_doc_number] => 20230205964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => LAYOUT METHOD AND RELATED NON-TRANSITORY COMPUTER-READABLE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/049486 [patent_app_country] => US [patent_app_date] => 2022-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3210 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18049486 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/049486
Layout method and related non-transitory computer-readable medium Oct 24, 2022 Issued
Array ( [id] => 18644377 [patent_doc_number] => 11768442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Method of determining control parameters of a device manufacturing process [patent_app_type] => utility [patent_app_number] => 17/973221 [patent_app_country] => US [patent_app_date] => 2022-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 40 [patent_no_of_words] => 26965 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17973221 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/973221
Method of determining control parameters of a device manufacturing process Oct 24, 2022 Issued
Array ( [id] => 18223244 [patent_doc_number] => 20230062238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => Pooling Processing Method and System Applied to Convolutional Neural Network [patent_app_type] => utility [patent_app_number] => 18/047716 [patent_app_country] => US [patent_app_date] => 2022-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18047716 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/047716
Pooling processing method and system applied to convolutional neural network Oct 18, 2022 Issued
Array ( [id] => 19303910 [patent_doc_number] => 20240232490 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => SYSTEM AND METHOD OF CONFIGURING INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/047926 [patent_app_country] => US [patent_app_date] => 2022-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18047926 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/047926
System and method of configuring integrated circuits Oct 18, 2022 Issued
Array ( [id] => 19303910 [patent_doc_number] => 20240232490 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => SYSTEM AND METHOD OF CONFIGURING INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/047926 [patent_app_country] => US [patent_app_date] => 2022-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18047926 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/047926
System and method of configuring integrated circuits Oct 18, 2022 Issued
Array ( [id] => 18307297 [patent_doc_number] => 20230111197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => PIN SHARING FOR PHOTONIC PROCESSORS [patent_app_type] => utility [patent_app_number] => 17/967314 [patent_app_country] => US [patent_app_date] => 2022-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8929 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17967314 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/967314
PIN SHARING FOR PHOTONIC PROCESSORS Oct 16, 2022 Pending
Array ( [id] => 18999549 [patent_doc_number] => 11916411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Modular charging system and wall-mounted charging device and modular power devices [patent_app_type] => utility [patent_app_number] => 17/963074 [patent_app_country] => US [patent_app_date] => 2022-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 42 [patent_no_of_words] => 10093 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17963074 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/963074
Modular charging system and wall-mounted charging device and modular power devices Oct 9, 2022 Issued
Array ( [id] => 20243173 [patent_doc_number] => 12423493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Synthetic loading of configurable logic devices [patent_app_type] => utility [patent_app_number] => 17/962272 [patent_app_country] => US [patent_app_date] => 2022-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5906 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17962272 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/962272
Synthetic loading of configurable logic devices Oct 6, 2022 Issued
Array ( [id] => 18169379 [patent_doc_number] => 20230035990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => Modular Charging System and Wall-Mounted Charging Device and Modular Power Devices [patent_app_type] => utility [patent_app_number] => 17/961225 [patent_app_country] => US [patent_app_date] => 2022-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10128 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17961225 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/961225
Modular charging system and wall-mounted charging device and modular power devices Oct 5, 2022 Issued
Array ( [id] => 19370831 [patent_doc_number] => 12062929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Modular charging system and wall-mounted charging device and modular power devices [patent_app_type] => utility [patent_app_number] => 17/960300 [patent_app_country] => US [patent_app_date] => 2022-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 42 [patent_no_of_words] => 10095 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17960300 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/960300
Modular charging system and wall-mounted charging device and modular power devices Oct 4, 2022 Issued
Array ( [id] => 20331805 [patent_doc_number] => 12462082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Satisfying circuit design constraints using a combination of machine learning models [patent_app_type] => utility [patent_app_number] => 17/959038 [patent_app_country] => US [patent_app_date] => 2022-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1151 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17959038 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/959038
Satisfying circuit design constraints using a combination of machine learning models Oct 2, 2022 Issued
Array ( [id] => 18281558 [patent_doc_number] => 20230097030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => SYSTEMS AND METHODS OF AUTOMATIC GENERATION OF INTEGRATED CIRCUIT IP BLOCKS [patent_app_type] => utility [patent_app_number] => 17/953378 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3689 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17953378 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/953378
Systems and methods of automatic generation of integrated circuit IP blocks Sep 26, 2022 Issued
Array ( [id] => 20583163 [patent_doc_number] => 12575426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Wafer-scale chip structure and method and system for designing the structure [patent_app_type] => utility [patent_app_number] => 17/935588 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 28 [patent_no_of_words] => 5025 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17935588 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/935588
Wafer-scale chip structure and method and system for designing the structure Sep 26, 2022 Issued
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