Phallaka Kik

Array ( [id] => 19071207 [patent_doc_number] => 20240105633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => WAFER-SCALE CHIP STRUCTURE AND METHOD AND SYSTEM FOR DESIGNING THE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/935588 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17935588 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19243635 [patent_doc_number] => 12014078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Apparatus and architecture of non-volatile memory module in parallel configuration [patent_app_type] => utility [patent_app_number] => 17/949845 [patent_app_country] => US [patent_app_date] => 2022-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8322 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17949845 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19053466 [patent_doc_number] => 20240095435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => ALGORITHMIC CIRCUIT DESIGN AUTOMATION [patent_app_type] => utility [patent_app_number] => 17/932538 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7500 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17932538 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18141967 [patent_doc_number] => 20230015810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => LAYOUT AND WIRING METHOD, COMPARISON METHOD, FABRICATION METHOD, DEVICE, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/945233 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17945233 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18141967 [patent_doc_number] => 20230015810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => LAYOUT AND WIRING METHOD, COMPARISON METHOD, FABRICATION METHOD, DEVICE, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/945233 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17945233 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18695157 [patent_doc_number] => 20230325577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => METHOD VERIFYING PROCESS PROXIMITY CORRECTION USING MACHINE LEARNING, AND SEMICONDUCTOR MANUFACTURING METHOD USING SAME [patent_app_type] => utility [patent_app_number] => 17/903070 [patent_app_country] => US [patent_app_date] => 2022-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8262 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17903070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18096100 [patent_doc_number] => 20220414441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => GENERAL PADDING SUPPORT FOR CONVOLUTION ON SYSTOLIC ARRAYS [patent_app_type] => utility [patent_app_number] => 17/902776 [patent_app_country] => US [patent_app_date] => 2022-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17902776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19872905 [patent_doc_number] => 12265767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => System and method for electronic circuit resimulation [patent_app_type] => utility [patent_app_number] => 17/893136 [patent_app_country] => US [patent_app_date] => 2022-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5641 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893136 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20079744 [patent_doc_number] => 12353813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Accounting for steady state noise in bit response superposition based eye diagram simulation [patent_app_type] => utility [patent_app_number] => 17/883357 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1183 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18957688 [patent_doc_number] => 20240046015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => LATENCY BALANCING OF PATHS IN MULTI-PROCESSOR COMPUTING ARCHITECTURE DESIGNS FOR DEADLOCK AVOIDANCE [patent_app_type] => utility [patent_app_number] => 17/818341 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12043 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17818341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20079744 [patent_doc_number] => 12353813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Accounting for steady state noise in bit response superposition based eye diagram simulation [patent_app_type] => utility [patent_app_number] => 17/883357 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1183 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18095966 [patent_doc_number] => 20220414307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => METHOD, APPARATUS, COMPUTER DEVICE, AND STORAGE MEDIUM FOR AUTOMATIC DESIGN OF ANALOG CIRCUITS BASED ON TREE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/880015 [patent_app_country] => US [patent_app_date] => 2022-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17880015 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17992240 [patent_doc_number] => 20220358277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => SYSTEM FOR DESIGNING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/815013 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6031 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815013 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18927922 [patent_doc_number] => 20240030926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => RETIMER WITH SLICER LEVEL ADJUSTMENT [patent_app_type] => utility [patent_app_number] => 17/873129 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18927922 [patent_doc_number] => 20240030926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => RETIMER WITH SLICER LEVEL ADJUSTMENT [patent_app_type] => utility [patent_app_number] => 17/873129 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18927922 [patent_doc_number] => 20240030926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => RETIMER WITH SLICER LEVEL ADJUSTMENT [patent_app_type] => utility [patent_app_number] => 17/873129 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18927922 [patent_doc_number] => 20240030926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => RETIMER WITH SLICER LEVEL ADJUSTMENT [patent_app_type] => utility [patent_app_number] => 17/873129 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20344605 [patent_doc_number] => 12468334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Clock signal realignment for emulation of a circuit design [patent_app_type] => utility [patent_app_number] => 17/870374 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4919 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870374 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18183021 [patent_doc_number] => 20230043751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => UNIFIED POWER FORMAT ANNOTATED RTL IMAGE RECOGNITION TO ACCELERATE LOW POWER VERIFICATION CONVERGENCE [patent_app_type] => utility [patent_app_number] => 17/868325 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17868325 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18554202 [patent_doc_number] => 20230252215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => SYSTEM AND METHOD FOR GENERATING A FLOORPLAN FOR A DIGITAL CIRCUIT USING REINFORCEMENT LEARNING [patent_app_type] => utility [patent_app_number] => 17/866270 [patent_app_country] => US [patent_app_date] => 2022-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10267 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17866270 [rel_patent_id] =>[rel_patent_doc_number] =>)