Search

Phallaka Kik

Examiner (ID: 11978, Phone: (571)272-1895 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2764, 2768, 2763, 2851, 2304
Total Applications
1951
Issued Applications
1745
Pending Applications
98
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18554202 [patent_doc_number] => 20230252215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => SYSTEM AND METHOD FOR GENERATING A FLOORPLAN FOR A DIGITAL CIRCUIT USING REINFORCEMENT LEARNING [patent_app_type] => utility [patent_app_number] => 17/866270 [patent_app_country] => US [patent_app_date] => 2022-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10267 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17866270 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/866270
System and method for generating a floorplan for a digital circuit using reinforcement learning Jul 14, 2022 Issued
Array ( [id] => 18554202 [patent_doc_number] => 20230252215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => SYSTEM AND METHOD FOR GENERATING A FLOORPLAN FOR A DIGITAL CIRCUIT USING REINFORCEMENT LEARNING [patent_app_type] => utility [patent_app_number] => 17/866270 [patent_app_country] => US [patent_app_date] => 2022-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10267 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17866270 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/866270
System and method for generating a floorplan for a digital circuit using reinforcement learning Jul 14, 2022 Issued
Array ( [id] => 18678313 [patent_doc_number] => 20230315961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => INFORMATION PROCESSING APPARATUS, INTEGRATED CIRCUIT, AND INFORMATION PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 17/860107 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17860107 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/860107
INFORMATION PROCESSING APPARATUS, INTEGRATED CIRCUIT, AND INFORMATION PROCESSING METHOD Jul 7, 2022 Pending
Array ( [id] => 18678313 [patent_doc_number] => 20230315961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => INFORMATION PROCESSING APPARATUS, INTEGRATED CIRCUIT, AND INFORMATION PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 17/860107 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17860107 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/860107
INFORMATION PROCESSING APPARATUS, INTEGRATED CIRCUIT, AND INFORMATION PROCESSING METHOD Jul 7, 2022 Pending
Array ( [id] => 18614629 [patent_doc_number] => 20230281366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => APPARATUS AND METHOD OF OPTIMIZING AN INTEGRTTED CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 17/858744 [patent_app_country] => US [patent_app_date] => 2022-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5680 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17858744 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/858744
Apparatus and method of optimizing an integrated circuit design Jul 5, 2022 Issued
Array ( [id] => 18614629 [patent_doc_number] => 20230281366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => APPARATUS AND METHOD OF OPTIMIZING AN INTEGRTTED CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 17/858744 [patent_app_country] => US [patent_app_date] => 2022-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5680 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17858744 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/858744
Apparatus and method of optimizing an integrated circuit design Jul 5, 2022 Issued
Array ( [id] => 20203341 [patent_doc_number] => 12406121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => 3D integrated circuit with enhanced debugging capability [patent_app_type] => utility [patent_app_number] => 17/810547 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5134 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17810547 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/810547
3D integrated circuit with enhanced debugging capability Jun 30, 2022 Issued
Array ( [id] => 20304424 [patent_doc_number] => 12450417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Semiconductor metal layer structure over cell region [patent_app_type] => utility [patent_app_number] => 17/856412 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 2294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856412 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/856412
Semiconductor metal layer structure over cell region Jun 30, 2022 Issued
Array ( [id] => 20304424 [patent_doc_number] => 12450417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Semiconductor metal layer structure over cell region [patent_app_type] => utility [patent_app_number] => 17/856412 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 2294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856412 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/856412
Semiconductor metal layer structure over cell region Jun 30, 2022 Issued
Array ( [id] => 19963723 [patent_doc_number] => 12333232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Method and system for processing simulation data [patent_app_type] => utility [patent_app_number] => 17/854086 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 0 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854086 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854086
Method and system for processing simulation data Jun 29, 2022 Issued
Array ( [id] => 18079841 [patent_doc_number] => 20220405453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => SYSTEMS AND METHODS FOR REDUCING CONGESTION ON NETWORK-ON-CHIP [patent_app_type] => utility [patent_app_number] => 17/854341 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854341 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854341
SYSTEMS AND METHODS FOR REDUCING CONGESTION ON NETWORK-ON-CHIP Jun 29, 2022 Pending
Array ( [id] => 19963723 [patent_doc_number] => 12333232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Method and system for processing simulation data [patent_app_type] => utility [patent_app_number] => 17/854086 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 0 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854086 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854086
Method and system for processing simulation data Jun 29, 2022 Issued
Array ( [id] => 20403753 [patent_doc_number] => 12493729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Stimuli-independent clock gating determination [patent_app_type] => utility [patent_app_number] => 17/853490 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 0 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17853490 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/853490
Stimuli-independent clock gating determination Jun 28, 2022 Issued
Array ( [id] => 20243177 [patent_doc_number] => 12423497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Layout repairing method and apparatus, computer device, and storage medium [patent_app_type] => utility [patent_app_number] => 17/807757 [patent_app_country] => US [patent_app_date] => 2022-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 1190 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17807757 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/807757
Layout repairing method and apparatus, computer device, and storage medium Jun 19, 2022 Issued
Array ( [id] => 17916075 [patent_doc_number] => 20220318471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => AUTONOMOUS CONTROL BOARD [patent_app_type] => utility [patent_app_number] => 17/842685 [patent_app_country] => US [patent_app_date] => 2022-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12603 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 501 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17842685 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/842685
AUTONOMOUS CONTROL BOARD Jun 15, 2022 Abandoned
Array ( [id] => 17916075 [patent_doc_number] => 20220318471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => AUTONOMOUS CONTROL BOARD [patent_app_type] => utility [patent_app_number] => 17/842685 [patent_app_country] => US [patent_app_date] => 2022-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12603 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 501 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17842685 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/842685
AUTONOMOUS CONTROL BOARD Jun 15, 2022 Abandoned
Array ( [id] => 17916075 [patent_doc_number] => 20220318471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => AUTONOMOUS CONTROL BOARD [patent_app_type] => utility [patent_app_number] => 17/842685 [patent_app_country] => US [patent_app_date] => 2022-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12603 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 501 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17842685 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/842685
AUTONOMOUS CONTROL BOARD Jun 15, 2022 Abandoned
Array ( [id] => 20359296 [patent_doc_number] => 12475295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Machine-learning-based power/ground (P/G) via removal [patent_app_type] => utility [patent_app_number] => 17/841400 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 29 [patent_no_of_words] => 3904 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841400 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/841400
Machine-learning-based power/ground (P/G) via removal Jun 14, 2022 Issued
Array ( [id] => 17885212 [patent_doc_number] => 20220300689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => INTEGRATED CIRCUIT DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT [patent_app_type] => utility [patent_app_number] => 17/836954 [patent_app_country] => US [patent_app_date] => 2022-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17836954 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/836954
Integrated circuit design method, system and computer program product Jun 8, 2022 Issued
Array ( [id] => 18487226 [patent_doc_number] => 20230214572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => CLOCK TREE LAYOUT AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/805921 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7026 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17805921 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/805921
Layout structure of clock tree circuitry and forming method thereof Jun 7, 2022 Issued
Menu