Search

Phallaka Kik

Examiner (ID: 11978, Phone: (571)272-1895 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2764, 2768, 2763, 2851, 2304
Total Applications
1951
Issued Applications
1745
Pending Applications
98
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18487226 [patent_doc_number] => 20230214572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => CLOCK TREE LAYOUT AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/805921 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7026 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17805921 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/805921
Layout structure of clock tree circuitry and forming method thereof Jun 7, 2022 Issued
Array ( [id] => 18819867 [patent_doc_number] => 20230394207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => Using Information Flow for Security Aware Design and Analysis [patent_app_type] => utility [patent_app_number] => 17/834815 [patent_app_country] => US [patent_app_date] => 2022-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7121 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834815 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/834815
Using information flow for security aware design and analysis Jun 6, 2022 Issued
Array ( [id] => 18393718 [patent_doc_number] => 20230161938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => Analog Information Model Object Class Definition [patent_app_type] => utility [patent_app_number] => 17/832830 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4198 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17832830 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/832830
Analog Information Model Object Class Definition Jun 5, 2022 Issued
Array ( [id] => 18067284 [patent_doc_number] => 20220398372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => DYNAMIC CLOCK TREE PLANNING USING FEEDTIMING COST [patent_app_type] => utility [patent_app_number] => 17/831367 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6714 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831367 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/831367
Dynamic clock tree planning using feedtiming cost Jun 1, 2022 Issued
Array ( [id] => 18561937 [patent_doc_number] => 11727183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement [patent_app_type] => utility [patent_app_number] => 17/828911 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 14313 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17828911 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/828911
Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement May 30, 2022 Issued
Array ( [id] => 20079740 [patent_doc_number] => 12353809 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Transformations for multicycle path prediction of clock signals [patent_app_type] => utility [patent_app_number] => 17/826055 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7413 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826055 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/826055
Transformations for multicycle path prediction of clock signals May 25, 2022 Issued
Array ( [id] => 17970390 [patent_doc_number] => 11487925 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-01 [patent_title] => Simulation method, apparatus, and device, and storage medium [patent_app_type] => utility [patent_app_number] => 17/664677 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 8614 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17664677 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/664677
Simulation method, apparatus, and device, and storage medium May 23, 2022 Issued
Array ( [id] => 17940734 [patent_doc_number] => 11475190 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-18 [patent_title] => Method for designing an integrated circuit and an integrated circuit designing system performing the same [patent_app_type] => utility [patent_app_number] => 17/750410 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7525 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750410 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/750410
Method for designing an integrated circuit and an integrated circuit designing system performing the same May 22, 2022 Issued
Array ( [id] => 17868922 [patent_doc_number] => 20220291659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => Synchronized Parallel Tile Computation for Large Area Lithography Simulation [patent_app_type] => utility [patent_app_number] => 17/750828 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750828 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/750828
Synchronized parallel tile computation for large area lithography simulation May 22, 2022 Issued
Array ( [id] => 18527953 [patent_doc_number] => 11714947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Method and layout of an integrated circuit [patent_app_type] => utility [patent_app_number] => 17/750201 [patent_app_country] => US [patent_app_date] => 2022-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6856 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750201 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/750201
Method and layout of an integrated circuit May 19, 2022 Issued
Array ( [id] => 19933982 [patent_doc_number] => 12307187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Circuit design having an improved clock tree [patent_app_type] => utility [patent_app_number] => 17/747797 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747797 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747797
Circuit design having an improved clock tree May 17, 2022 Issued
Array ( [id] => 17839821 [patent_doc_number] => 20220277126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => SYSTEMS AND METHODS FOR OBFUSCATING A CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 17/745814 [patent_app_country] => US [patent_app_date] => 2022-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 67220 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17745814 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/745814
SYSTEMS AND METHODS FOR OBFUSCATING A CIRCUIT DESIGN May 15, 2022 Pending
Array ( [id] => 19677446 [patent_doc_number] => 12189302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Computational metrology [patent_app_type] => utility [patent_app_number] => 17/738093 [patent_app_country] => US [patent_app_date] => 2022-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 37294 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17738093 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/738093
Computational metrology May 5, 2022 Issued
Array ( [id] => 18430723 [patent_doc_number] => 11675945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Reset crossing and clock crossing interface for integrated circuit generation [patent_app_type] => utility [patent_app_number] => 17/734332 [patent_app_country] => US [patent_app_date] => 2022-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 19022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17734332 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/734332
Reset crossing and clock crossing interface for integrated circuit generation May 1, 2022 Issued
Array ( [id] => 18742103 [patent_doc_number] => 20230351085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => DETECTING INSTABILITY IN COMBINATIONAL LOOPS IN ELECTRONIC CIRCUIT DESIGNS [patent_app_type] => utility [patent_app_number] => 17/733266 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17733266 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/733266
Detecting instability in combinational loops in electronic circuit designs Apr 28, 2022 Issued
Array ( [id] => 18742103 [patent_doc_number] => 20230351085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => DETECTING INSTABILITY IN COMBINATIONAL LOOPS IN ELECTRONIC CIRCUIT DESIGNS [patent_app_type] => utility [patent_app_number] => 17/733266 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17733266 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/733266
Detecting instability in combinational loops in electronic circuit designs Apr 28, 2022 Issued
Array ( [id] => 17948168 [patent_doc_number] => 20220335187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => MULTI-CYCLE TEST GENERATION AND SOURCE-BASED SIMULATION [patent_app_type] => utility [patent_app_number] => 17/721264 [patent_app_country] => US [patent_app_date] => 2022-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9752 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17721264 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/721264
Multi-cycle test generation and source-based simulation Apr 13, 2022 Issued
Array ( [id] => 17738695 [patent_doc_number] => 20220224157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => WIRELESS CHARGING OF ELECTRONIC DEVICES [patent_app_type] => utility [patent_app_number] => 17/708365 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17708365 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/708365
WIRELESS CHARGING OF ELECTRONIC DEVICES Mar 29, 2022 Abandoned
Array ( [id] => 17916266 [patent_doc_number] => 20220318662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => SYSTEM AND METHOD FOR MAPPING QUANTUM CIRCUITS TO IONS IN A STORAGE RING QUANTUM COMPUTER ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/706741 [patent_app_country] => US [patent_app_date] => 2022-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6604 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17706741 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/706741
SYSTEM AND METHOD FOR MAPPING QUANTUM CIRCUITS TO IONS IN A STORAGE RING QUANTUM COMPUTER ARCHITECTURE Mar 28, 2022 Pending
Array ( [id] => 18124681 [patent_doc_number] => 20230010293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 17/656759 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6371 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17656759 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/656759
Semiconductor integrated circuit design method and apparatus Mar 27, 2022 Issued
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