Search

Phallaka Kik

Examiner (ID: 18158)

Most Active Art Unit
2851
Art Unit(s)
2851, 2763, 2764, 2304, 2825, 2768
Total Applications
1948
Issued Applications
1741
Pending Applications
98
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20304420 [patent_doc_number] => 12450413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Systems and methods for assembling and developing an SoC efficiently using templates and designer input data [patent_app_type] => utility [patent_app_number] => 17/671520 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 32 [patent_no_of_words] => 43413 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17671520 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/671520
Systems and methods for assembling and developing an SoC efficiently using templates and designer input data Feb 13, 2022 Issued
Array ( [id] => 19900679 [patent_doc_number] => 12278624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Logic circuit for providing a signal value after a predetermined time period and method of using same [patent_app_type] => utility [patent_app_number] => 17/670128 [patent_app_country] => US [patent_app_date] => 2022-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17670128 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/670128
Logic circuit for providing a signal value after a predetermined time period and method of using same Feb 10, 2022 Issued
Array ( [id] => 17629503 [patent_doc_number] => 20220164518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => ENGINEERING CHANGE ORDER CELL STRUCTURE HAVING ALWAYS-ON TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/670370 [patent_app_country] => US [patent_app_date] => 2022-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9906 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17670370 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/670370
Engineering change order cell structure having always-on transistor Feb 10, 2022 Issued
Array ( [id] => 19924381 [patent_doc_number] => 12298661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Mask design method and storage medium thereof [patent_app_type] => utility [patent_app_number] => 17/668489 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 830 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17668489 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/668489
Mask design method and storage medium thereof Feb 9, 2022 Issued
Array ( [id] => 19720724 [patent_doc_number] => 12206272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Electric vehicle charging dynamic scheduling [patent_app_type] => utility [patent_app_number] => 17/668147 [patent_app_country] => US [patent_app_date] => 2022-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4412 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17668147 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/668147
Electric vehicle charging dynamic scheduling Feb 8, 2022 Issued
Array ( [id] => 17778964 [patent_doc_number] => 20220245314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => CIRCUIT DESIGN VALIDATION TOOL FOR RADIATION-HARDENED DESIGN [patent_app_type] => utility [patent_app_number] => 17/586516 [patent_app_country] => US [patent_app_date] => 2022-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9943 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17586516 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/586516
Circuit design validation tool for radiation-hardened design Jan 26, 2022 Issued
Array ( [id] => 17599501 [patent_doc_number] => 20220149075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => MULTI VERSION LIBRARY CELL HANDLING AND INTEGRATED CIRCUIT STRUCTURES FABRICATED THEREFROM [patent_app_type] => utility [patent_app_number] => 17/585101 [patent_app_country] => US [patent_app_date] => 2022-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11820 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17585101 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/585101
Multi version library cell handling and integrated circuit structures fabricated therefrom Jan 25, 2022 Issued
Array ( [id] => 17698245 [patent_doc_number] => 11371966 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-28 [patent_title] => Digital twin model inversion for testing [patent_app_type] => utility [patent_app_number] => 17/585299 [patent_app_country] => US [patent_app_date] => 2022-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8909 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17585299 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/585299
Digital twin model inversion for testing Jan 25, 2022 Issued
Array ( [id] => 17998844 [patent_doc_number] => 11499945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Digital twin model inversion for testing [patent_app_type] => utility [patent_app_number] => 17/585343 [patent_app_country] => US [patent_app_date] => 2022-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8909 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17585343 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/585343
Digital twin model inversion for testing Jan 25, 2022 Issued
Array ( [id] => 18184298 [patent_doc_number] => 20230045028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => CHARGING SYSTEM, METHOD AND DEVICE FOR CONTROLLING CHARGING SYSTEM, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/583979 [patent_app_country] => US [patent_app_date] => 2022-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17583979 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/583979
Charging system, method and device for controlling charging system, and electronic device Jan 24, 2022 Issued
Array ( [id] => 18487220 [patent_doc_number] => 20230214566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => DYNAMIC CONTROL OF COVERAGE BY A VERIFICATION TESTBENCH [patent_app_type] => utility [patent_app_number] => 17/567977 [patent_app_country] => US [patent_app_date] => 2022-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17567977 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/567977
Dynamic control of coverage by a verification testbench Jan 3, 2022 Issued
Array ( [id] => 17707218 [patent_doc_number] => 20220207224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => DETECTING SHARED RESCOURCES AND COUPLING FACTORS [patent_app_type] => utility [patent_app_number] => 17/564117 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12999 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564117 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564117
Detecting shared rescources and coupling factors Dec 27, 2021 Issued
Array ( [id] => 18471673 [patent_doc_number] => 20230205959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => HYBRID SYNCHRONOUS AND ASYNCHRONOUS CONTROL FOR SCAN-BASED TESTING [patent_app_type] => utility [patent_app_number] => 17/646184 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8516 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17646184 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/646184
Hybrid synchronous and asynchronous control for scan-based testing Dec 27, 2021 Issued
Array ( [id] => 17535707 [patent_doc_number] => 20220114316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => DYNAMIC LOADLINES FOR PROGRAMMABLE FABRIC DEVICES [patent_app_type] => utility [patent_app_number] => 17/559607 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559607 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559607
Dynamic loadlines for programmable fabric devices Dec 21, 2021 Issued
Array ( [id] => 18720396 [patent_doc_number] => 11797742 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-24 [patent_title] => Power aware real number modeling in dynamic verification of mixed-signal integrated circuit design [patent_app_type] => utility [patent_app_number] => 17/559901 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 19120 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559901 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559901
Power aware real number modeling in dynamic verification of mixed-signal integrated circuit design Dec 21, 2021 Issued
Array ( [id] => 17535707 [patent_doc_number] => 20220114316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => DYNAMIC LOADLINES FOR PROGRAMMABLE FABRIC DEVICES [patent_app_type] => utility [patent_app_number] => 17/559607 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559607 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559607
Dynamic loadlines for programmable fabric devices Dec 21, 2021 Issued
Array ( [id] => 18839319 [patent_doc_number] => 11847393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Computing device and method for developing a system model utilizing a simulation assessment module [patent_app_type] => utility [patent_app_number] => 17/552468 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 11580 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17552468 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/552468
Computing device and method for developing a system model utilizing a simulation assessment module Dec 15, 2021 Issued
Array ( [id] => 17675324 [patent_doc_number] => 20220188491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => DESIGN TO FABRICATED LAYOUT CORRELATION [patent_app_type] => utility [patent_app_number] => 17/545572 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17545572 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/545572
Fabricated layout correlation Dec 7, 2021 Issued
Array ( [id] => 17659570 [patent_doc_number] => 20220180035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => AUTOMATIC SEQUENTIAL RETRY ON COMPILATION FAILURE [patent_app_type] => utility [patent_app_number] => 17/541886 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17541886 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/541886
Automatic sequential retry on compilation failure Dec 2, 2021 Issued
Array ( [id] => 18839320 [patent_doc_number] => 11847394 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => System and method for using interface protection parameters [patent_app_type] => utility [patent_app_number] => 17/540236 [patent_app_country] => US [patent_app_date] => 2021-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5816 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17540236 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/540236
System and method for using interface protection parameters Dec 1, 2021 Issued
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