
Phallaka Kik
Examiner (ID: 8609, Phone: (571)272-1895 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2768, 2851, 2763, 2304, 2825, 2764 |
| Total Applications | 1982 |
| Issued Applications | 1763 |
| Pending Applications | 103 |
| Abandoned Applications | 144 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17535707
[patent_doc_number] => 20220114316
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-14
[patent_title] => DYNAMIC LOADLINES FOR PROGRAMMABLE FABRIC DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/559607
[patent_app_country] => US
[patent_app_date] => 2021-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4717
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559607
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/559607 | Dynamic loadlines for programmable fabric devices | Dec 21, 2021 | Issued |
Array
(
[id] => 18839319
[patent_doc_number] => 11847393
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-19
[patent_title] => Computing device and method for developing a system model utilizing a simulation assessment module
[patent_app_type] => utility
[patent_app_number] => 17/552468
[patent_app_country] => US
[patent_app_date] => 2021-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 11580
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17552468
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/552468 | Computing device and method for developing a system model utilizing a simulation assessment module | Dec 15, 2021 | Issued |
Array
(
[id] => 17675324
[patent_doc_number] => 20220188491
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-16
[patent_title] => DESIGN TO FABRICATED LAYOUT CORRELATION
[patent_app_type] => utility
[patent_app_number] => 17/545572
[patent_app_country] => US
[patent_app_date] => 2021-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5236
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17545572
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/545572 | Fabricated layout correlation | Dec 7, 2021 | Issued |
Array
(
[id] => 17659570
[patent_doc_number] => 20220180035
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-09
[patent_title] => AUTOMATIC SEQUENTIAL RETRY ON COMPILATION FAILURE
[patent_app_type] => utility
[patent_app_number] => 17/541886
[patent_app_country] => US
[patent_app_date] => 2021-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13074
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17541886
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/541886 | Automatic sequential retry on compilation failure | Dec 2, 2021 | Issued |
Array
(
[id] => 18839320
[patent_doc_number] => 11847394
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-19
[patent_title] => System and method for using interface protection parameters
[patent_app_type] => utility
[patent_app_number] => 17/540236
[patent_app_country] => US
[patent_app_date] => 2021-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 5816
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17540236
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/540236 | System and method for using interface protection parameters | Dec 1, 2021 | Issued |
Array
(
[id] => 19841864
[patent_doc_number] => 12254254
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-18
[patent_title] => Circuits and techniques for predicting failure of circuits based on stress origination metrics and stress victim events
[patent_app_type] => utility
[patent_app_number] => 17/457216
[patent_app_country] => US
[patent_app_date] => 2021-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6812
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457216
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/457216 | Circuits and techniques for predicting failure of circuits based on stress origination metrics and stress victim events | Nov 30, 2021 | Issued |
Array
(
[id] => 18839318
[patent_doc_number] => 11847392
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2023-12-19
[patent_title] => Method, product, and system for dynamic design switching for high performance mixed signal simulation
[patent_app_type] => utility
[patent_app_number] => 17/457017
[patent_app_country] => US
[patent_app_date] => 2021-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5110
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457017
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/457017 | Method, product, and system for dynamic design switching for high performance mixed signal simulation | Nov 29, 2021 | Issued |
Array
(
[id] => 18432024
[patent_doc_number] => 11677259
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-13
[patent_title] => Power backup architecture using capacitor
[patent_app_type] => utility
[patent_app_number] => 17/534168
[patent_app_country] => US
[patent_app_date] => 2021-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 11311
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17534168
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/534168 | Power backup architecture using capacitor | Nov 22, 2021 | Issued |
Array
(
[id] => 18415122
[patent_doc_number] => 11669665
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2023-06-06
[patent_title] => Application-specific integrated circuit (ASIC) synthesis based on lookup table (LUT) mapping and optimization
[patent_app_type] => utility
[patent_app_number] => 17/527911
[patent_app_country] => US
[patent_app_date] => 2021-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7775
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17527911
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/527911 | Application-specific integrated circuit (ASIC) synthesis based on lookup table (LUT) mapping and optimization | Nov 15, 2021 | Issued |
Array
(
[id] => 18668821
[patent_doc_number] => 11775725
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-03
[patent_title] => System and computer program product for integrated circuit design
[patent_app_type] => utility
[patent_app_number] => 17/527967
[patent_app_country] => US
[patent_app_date] => 2021-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 11633
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17527967
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/527967 | System and computer program product for integrated circuit design | Nov 15, 2021 | Issued |
Array
(
[id] => 18902148
[patent_doc_number] => 20240017633
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-18
[patent_title] => CHARGING DEVICE AND METHOD FOR ELECTRICALLY CHARGING AN ELECTRIC VEHICLE
[patent_app_type] => utility
[patent_app_number] => 18/036032
[patent_app_country] => US
[patent_app_date] => 2021-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13374
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18036032
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/036032 | CHARGING DEVICE AND METHOD FOR ELECTRICALLY CHARGING AN ELECTRIC VEHICLE | Nov 9, 2021 | Pending |
Array
(
[id] => 18346918
[patent_doc_number] => 20230135028
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-04
[patent_title] => CHARGING SYSTEM, VEHICLE INCLUDING A CHARGING SYSTEM, AND CHARGING METHOD
[patent_app_type] => utility
[patent_app_number] => 17/518210
[patent_app_country] => US
[patent_app_date] => 2021-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5578
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518210
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/518210 | Charging system, vehicle including a charging system, and charging method | Nov 2, 2021 | Issued |
Array
(
[id] => 17401866
[patent_doc_number] => 20220043956
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-10
[patent_title] => METHODS FOR ENGINEERING INTEGRATED CIRCUIT DESIGN AND DEVELOPMENT
[patent_app_type] => utility
[patent_app_number] => 17/510315
[patent_app_country] => US
[patent_app_date] => 2021-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 56235
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510315
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/510315 | Methods for engineering integrated circuit design and development | Oct 24, 2021 | Issued |
Array
(
[id] => 17401863
[patent_doc_number] => 20220043953
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-10
[patent_title] => AUTOMATED CIRCUIT GENERATION
[patent_app_type] => utility
[patent_app_number] => 17/507504
[patent_app_country] => US
[patent_app_date] => 2021-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 64558
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17507504
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/507504 | Automated circuit generation | Oct 20, 2021 | Issued |
Array
(
[id] => 18807912
[patent_doc_number] => 20230382245
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => ACTIVE PAIRING METHOD AND DEVICE FOR WIRELESS LAN-BASED SMART CHARGING OR SMART CHARGING AND DISCHARGING
[patent_app_type] => utility
[patent_app_number] => 18/032615
[patent_app_country] => US
[patent_app_date] => 2021-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12473
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18032615
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/032615 | ACTIVE PAIRING METHOD AND DEVICE FOR WIRELESS LAN-BASED SMART CHARGING OR SMART CHARGING AND DISCHARGING | Oct 20, 2021 | Pending |
Array
(
[id] => 19029053
[patent_doc_number] => 11928412
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-12
[patent_title] => Method
[patent_app_type] => utility
[patent_app_number] => 17/505681
[patent_app_country] => US
[patent_app_date] => 2021-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4052
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17505681
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/505681 | Method | Oct 19, 2021 | Issued |
Array
(
[id] => 17550457
[patent_doc_number] => 20220121799
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-21
[patent_title] => TRANSISTOR- LEVEL DEFECT COVERAGE AND DEFECT SIMULATION
[patent_app_type] => utility
[patent_app_number] => 17/450899
[patent_app_country] => US
[patent_app_date] => 2021-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13402
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17450899
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/450899 | Transistor--level defect coverage and defect simulation | Oct 13, 2021 | Issued |
Array
(
[id] => 18668818
[patent_doc_number] => 11775722
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-03
[patent_title] => Systems and methods for obfuscating a circuit design
[patent_app_type] => utility
[patent_app_number] => 17/493576
[patent_app_country] => US
[patent_app_date] => 2021-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 78
[patent_figures_cnt] => 81
[patent_no_of_words] => 67185
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17493576
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/493576 | Systems and methods for obfuscating a circuit design | Oct 3, 2021 | Issued |
Array
(
[id] => 18447336
[patent_doc_number] => 11682915
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-20
[patent_title] => Charge coupler and method for autonomously charging vehicle batteries
[patent_app_type] => utility
[patent_app_number] => 17/486298
[patent_app_country] => US
[patent_app_date] => 2021-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 20
[patent_no_of_words] => 18146
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17486298
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/486298 | Charge coupler and method for autonomously charging vehicle batteries | Sep 26, 2021 | Issued |
Array
(
[id] => 17338359
[patent_doc_number] => 20220004690
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-06
[patent_title] => Verification of Hardware Design for Data Transformation Pipeline
[patent_app_type] => utility
[patent_app_number] => 17/478739
[patent_app_country] => US
[patent_app_date] => 2021-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 25021
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17478739
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/478739 | Verification of hardware design for data transformation pipeline | Sep 16, 2021 | Issued |