
Phat X. Cao
Examiner (ID: 7067)
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2508, 2817, 2814 |
| Total Applications | 1687 |
| Issued Applications | 1251 |
| Pending Applications | 92 |
| Abandoned Applications | 373 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19679395
[patent_doc_number] => 12191268
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2025-01-07
[patent_title] => Integrated circuit packages having stress-relieving features
[patent_app_type] => utility
[patent_app_number] => 18/778322
[patent_app_country] => US
[patent_app_date] => 2024-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 17
[patent_no_of_words] => 8780
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778322
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/778322 | Integrated circuit packages having stress-relieving features | Jul 18, 2024 | Issued |
Array
(
[id] => 19500356
[patent_doc_number] => 20240339374
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-10
[patent_title] => ARRAY OF HEAT-SINKED POWER SEMICONDUCTORS
[patent_app_type] => utility
[patent_app_number] => 18/745743
[patent_app_country] => US
[patent_app_date] => 2024-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3189
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18745743
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/745743 | ARRAY OF HEAT-SINKED POWER SEMICONDUCTORS | Jun 16, 2024 | Pending |
Array
(
[id] => 19484149
[patent_doc_number] => 20240332191
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => Interconnect Structure and Method of Forming Same
[patent_app_type] => utility
[patent_app_number] => 18/742056
[patent_app_country] => US
[patent_app_date] => 2024-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5380
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742056
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/742056 | Interconnect Structure and Method of Forming Same | Jun 12, 2024 | Pending |
Array
(
[id] => 19468058
[patent_doc_number] => 20240321728
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 18/733705
[patent_app_country] => US
[patent_app_date] => 2024-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8203
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733705
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/733705 | Semiconductor package | Jun 3, 2024 | Issued |
Array
(
[id] => 19392883
[patent_doc_number] => 20240282753
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-22
[patent_title] => DEVICE INCLUDING FIRST STRUCTURE HAVING PERIPHERAL CIRCUIT AND SECOND STRUCTURE HAVING GATE LAYERS
[patent_app_type] => utility
[patent_app_number] => 18/634014
[patent_app_country] => US
[patent_app_date] => 2024-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12247
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 239
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634014
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/634014 | DEVICE INCLUDING FIRST STRUCTURE HAVING PERIPHERAL CIRCUIT AND SECOND STRUCTURE HAVING GATE LAYERS | Apr 11, 2024 | Pending |
Array
(
[id] => 20305463
[patent_doc_number] => 12451464
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-21
[patent_title] => Mitigating thermal impacts on adjacent stacked semiconductor devices
[patent_app_type] => utility
[patent_app_number] => 18/633330
[patent_app_country] => US
[patent_app_date] => 2024-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 0
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18633330
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/633330 | Mitigating thermal impacts on adjacent stacked semiconductor devices | Apr 10, 2024 | Issued |
Array
(
[id] => 19305721
[patent_doc_number] => 20240234301
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-11
[patent_title] => SEMICONDUCTOR STRUCTURE WITH VIA EXTENDING ACROSS ADJACENT CONDUCTIVE LINES
[patent_app_type] => utility
[patent_app_number] => 18/616195
[patent_app_country] => US
[patent_app_date] => 2024-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12034
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18616195
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/616195 | SEMICONDUCTOR STRUCTURE WITH VIA EXTENDING ACROSS ADJACENT CONDUCTIVE LINES | Mar 25, 2024 | Pending |
Array
(
[id] => 19349467
[patent_doc_number] => 20240258431
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-01
[patent_title] => Semiconductor Device And Manufacturing Method Thereof
[patent_app_type] => utility
[patent_app_number] => 18/603429
[patent_app_country] => US
[patent_app_date] => 2024-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13316
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18603429
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/603429 | Semiconductor Device And Manufacturing Method Thereof | Mar 12, 2024 | Pending |
Array
(
[id] => 19842765
[patent_doc_number] => 12255165
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-18
[patent_title] => Electronic package and carrier thereof and method for manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 18/602396
[patent_app_country] => US
[patent_app_date] => 2024-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 3738
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602396
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/602396 | Electronic package and carrier thereof and method for manufacturing the same | Mar 11, 2024 | Issued |
Array
(
[id] => 19364244
[patent_doc_number] => 20240266278
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-08
[patent_title] => INTERCONNECTION STRUCTURE FOR INTEGRATED CIRCUIT PACKAGE
[patent_app_type] => utility
[patent_app_number] => 18/436946
[patent_app_country] => US
[patent_app_date] => 2024-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3306
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18436946
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/436946 | INTERCONNECTION STRUCTURE FOR INTEGRATED CIRCUIT PACKAGE | Feb 7, 2024 | Pending |
Array
(
[id] => 19206259
[patent_doc_number] => 20240178158
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-30
[patent_title] => PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/434698
[patent_app_country] => US
[patent_app_date] => 2024-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12010
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18434698
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/434698 | PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME | Feb 5, 2024 | Pending |
Array
(
[id] => 19191595
[patent_doc_number] => 20240170508
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-23
[patent_title] => PIXEL DEVICE LAYOUT TO REDUCE PIXEL NOISE
[patent_app_type] => utility
[patent_app_number] => 18/427963
[patent_app_country] => US
[patent_app_date] => 2024-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13893
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18427963
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/427963 | PIXEL DEVICE LAYOUT TO REDUCE PIXEL NOISE | Jan 30, 2024 | Pending |
Array
(
[id] => 19191484
[patent_doc_number] => 20240170397
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-23
[patent_title] => INTERCONNECT LEVEL WITH HIGH RESISTANCE LAYER AND METHOD OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/420884
[patent_app_country] => US
[patent_app_date] => 2024-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10279
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420884
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/420884 | INTERCONNECT LEVEL WITH HIGH RESISTANCE LAYER AND METHOD OF FORMING THE SAME | Jan 23, 2024 | Pending |
Array
(
[id] => 19071311
[patent_doc_number] => 20240105737
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-28
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/534908
[patent_app_country] => US
[patent_app_date] => 2023-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 33279
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -2
[patent_words_short_claim] => 726
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18534908
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/534908 | Display device | Dec 10, 2023 | Issued |
Array
(
[id] => 19358391
[patent_doc_number] => 12058874
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-08-06
[patent_title] => Universal network-attached memory architecture
[patent_app_type] => utility
[patent_app_number] => 18/528702
[patent_app_country] => US
[patent_app_date] => 2023-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 4659
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18528702
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/528702 | Universal network-attached memory architecture | Dec 3, 2023 | Issued |
Array
(
[id] => 19038306
[patent_doc_number] => 20240088121
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-14
[patent_title] => PATCH ACCOMMODATING EMBEDDED DIES HAVING DIFFERENT THICKNESSES
[patent_app_type] => utility
[patent_app_number] => 18/511641
[patent_app_country] => US
[patent_app_date] => 2023-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8013
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18511641
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/511641 | PATCH ACCOMMODATING EMBEDDED DIES HAVING DIFFERENT THICKNESSES | Nov 15, 2023 | Pending |
Array
(
[id] => 19328840
[patent_doc_number] => 12046529
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-23
[patent_title] => Array of heat-sinked power semiconductors
[patent_app_type] => utility
[patent_app_number] => 18/388873
[patent_app_country] => US
[patent_app_date] => 2023-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 3211
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18388873
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/388873 | Array of heat-sinked power semiconductors | Nov 12, 2023 | Issued |
Array
(
[id] => 18977248
[patent_doc_number] => 20240057340
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-15
[patent_title] => MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS
[patent_app_type] => utility
[patent_app_number] => 18/491711
[patent_app_country] => US
[patent_app_date] => 2023-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12162
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 14
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18491711
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/491711 | MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS | Oct 19, 2023 | Pending |
Array
(
[id] => 19384605
[patent_doc_number] => 20240274475
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-15
[patent_title] => HYBRID-CHANNEL NANO-SHEET FETS
[patent_app_type] => utility
[patent_app_number] => 18/371871
[patent_app_country] => US
[patent_app_date] => 2023-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5353
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18371871
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/371871 | HYBRID-CHANNEL NANO-SHEET FETS | Sep 21, 2023 | Pending |
Array
(
[id] => 18865939
[patent_doc_number] => 20230420376
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-28
[patent_title] => MICROELECTRONIC STRUCTURES INCLUDING BRIDGES
[patent_app_type] => utility
[patent_app_number] => 18/462600
[patent_app_country] => US
[patent_app_date] => 2023-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 41295
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18462600
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/462600 | Microelectronic structures including bridges | Sep 6, 2023 | Issued |