Search

Phat X. Cao

Examiner (ID: 1949, Phone: (571)272-1703 , Office: P/2817 )

Most Active Art Unit
2814
Art Unit(s)
2814, 2817, 2508
Total Applications
1670
Issued Applications
1258
Pending Applications
65
Abandoned Applications
373

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19679395 [patent_doc_number] => 12191268 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-07 [patent_title] => Integrated circuit packages having stress-relieving features [patent_app_type] => utility [patent_app_number] => 18/778322 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 8780 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778322 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/778322
Integrated circuit packages having stress-relieving features Jul 18, 2024 Issued
Array ( [id] => 19500356 [patent_doc_number] => 20240339374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => ARRAY OF HEAT-SINKED POWER SEMICONDUCTORS [patent_app_type] => utility [patent_app_number] => 18/745743 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3189 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18745743 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/745743
ARRAY OF HEAT-SINKED POWER SEMICONDUCTORS Jun 16, 2024 Pending
Array ( [id] => 20532253 [patent_doc_number] => 12550706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Interconnect structure and method of forming same [patent_app_type] => utility [patent_app_number] => 18/742056 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742056 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/742056
Interconnect structure and method of forming same Jun 12, 2024 Issued
Array ( [id] => 19468058 [patent_doc_number] => 20240321728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/733705 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8203 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733705 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733705
Semiconductor package Jun 3, 2024 Issued
Array ( [id] => 20598270 [patent_doc_number] => 12582011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Device including first structure having peripheral circuit and second structure having gate layers [patent_app_type] => utility [patent_app_number] => 18/634014 [patent_app_country] => US [patent_app_date] => 2024-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 29 [patent_no_of_words] => 7846 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 393 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634014 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/634014
Device including first structure having peripheral circuit and second structure having gate layers Apr 11, 2024 Issued
Array ( [id] => 20305463 [patent_doc_number] => 12451464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Mitigating thermal impacts on adjacent stacked semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/633330 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18633330 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/633330
Mitigating thermal impacts on adjacent stacked semiconductor devices Apr 10, 2024 Issued
Array ( [id] => 19305721 [patent_doc_number] => 20240234301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => SEMICONDUCTOR STRUCTURE WITH VIA EXTENDING ACROSS ADJACENT CONDUCTIVE LINES [patent_app_type] => utility [patent_app_number] => 18/616195 [patent_app_country] => US [patent_app_date] => 2024-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12034 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18616195 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/616195
Semiconductor structure with via extending across adjacent conductive lines Mar 25, 2024 Issued
Array ( [id] => 19842765 [patent_doc_number] => 12255165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Electronic package and carrier thereof and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/602396 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 3738 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602396 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/602396
Electronic package and carrier thereof and method for manufacturing the same Mar 11, 2024 Issued
Array ( [id] => 19191484 [patent_doc_number] => 20240170397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => INTERCONNECT LEVEL WITH HIGH RESISTANCE LAYER AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/420884 [patent_app_country] => US [patent_app_date] => 2024-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420884 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/420884
Interconnect level with high resistance layer and method of forming the same Jan 23, 2024 Issued
Array ( [id] => 19071311 [patent_doc_number] => 20240105737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/534908 [patent_app_country] => US [patent_app_date] => 2023-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 726 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18534908 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/534908
Display device Dec 10, 2023 Issued
Array ( [id] => 19358391 [patent_doc_number] => 12058874 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-08-06 [patent_title] => Universal network-attached memory architecture [patent_app_type] => utility [patent_app_number] => 18/528702 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4659 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18528702 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/528702
Universal network-attached memory architecture Dec 3, 2023 Issued
Array ( [id] => 19038306 [patent_doc_number] => 20240088121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => PATCH ACCOMMODATING EMBEDDED DIES HAVING DIFFERENT THICKNESSES [patent_app_type] => utility [patent_app_number] => 18/511641 [patent_app_country] => US [patent_app_date] => 2023-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8013 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18511641 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/511641
PATCH ACCOMMODATING EMBEDDED DIES HAVING DIFFERENT THICKNESSES Nov 15, 2023 Pending
Array ( [id] => 19328840 [patent_doc_number] => 12046529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Array of heat-sinked power semiconductors [patent_app_type] => utility [patent_app_number] => 18/388873 [patent_app_country] => US [patent_app_date] => 2023-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3211 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18388873 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/388873
Array of heat-sinked power semiconductors Nov 12, 2023 Issued
Array ( [id] => 19384605 [patent_doc_number] => 20240274475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => HYBRID-CHANNEL NANO-SHEET FETS [patent_app_type] => utility [patent_app_number] => 18/371871 [patent_app_country] => US [patent_app_date] => 2023-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18371871 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/371871
Hybrid-channel nano-sheet FETs Sep 21, 2023 Issued
Array ( [id] => 18865939 [patent_doc_number] => 20230420376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => MICROELECTRONIC STRUCTURES INCLUDING BRIDGES [patent_app_type] => utility [patent_app_number] => 18/462600 [patent_app_country] => US [patent_app_date] => 2023-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 41295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18462600 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/462600
Microelectronic structures including bridges Sep 6, 2023 Issued
Array ( [id] => 18849104 [patent_doc_number] => 20230411508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => NITRIDE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 18/451863 [patent_app_country] => US [patent_app_date] => 2023-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18451863 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/451863
Nitride semiconductor device and fabrication method therefor Aug 17, 2023 Issued
Array ( [id] => 18821055 [patent_doc_number] => 20230395396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR INTERCONNECT STRUCTURE AND SEMICONDUCTOR STRUCTURE THEREOF [patent_app_type] => utility [patent_app_number] => 18/235456 [patent_app_country] => US [patent_app_date] => 2023-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4549 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18235456 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/235456
METHOD FOR FABRICATING SEMICONDUCTOR INTERCONNECT STRUCTURE AND SEMICONDUCTOR STRUCTURE THEREOF Aug 17, 2023 Pending
Array ( [id] => 20189837 [patent_doc_number] => 12400962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Liner-free conductive structures with anchor points [patent_app_type] => utility [patent_app_number] => 18/232722 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 3444 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18232722 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/232722
Liner-free conductive structures with anchor points Aug 9, 2023 Issued
Array ( [id] => 18906021 [patent_doc_number] => 20240021506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => Semiconductor Package Having Multiple Substrates [patent_app_type] => utility [patent_app_number] => 18/447008 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9099 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447008 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447008
Semiconductor package having multiple substrates Aug 8, 2023 Issued
Array ( [id] => 18774284 [patent_doc_number] => 20230369115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => PACKAGE STRUCTURE WITH FAN-OUT FEATURE [patent_app_type] => utility [patent_app_number] => 18/360581 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7537 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360581 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360581
Package structure with fan-out feature Jul 26, 2023 Issued
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