Search

Phat X. Cao

Examiner (ID: 7067)

Most Active Art Unit
2814
Art Unit(s)
2508, 2817, 2814
Total Applications
1687
Issued Applications
1251
Pending Applications
92
Abandoned Applications
373

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19552852 [patent_doc_number] => 12136564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-05 [patent_title] => Superstrate and method of making it [patent_app_type] => utility [patent_app_number] => 16/834465 [patent_app_country] => US [patent_app_date] => 2020-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5278 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16834465 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/834465
Superstrate and method of making it Mar 29, 2020 Issued
Array ( [id] => 16180303 [patent_doc_number] => 20200227272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => Interconnect Structure with Porous Low K Film [patent_app_type] => utility [patent_app_number] => 16/831336 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4110 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16831336 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/831336
Interconnect Structure with Porous Low K Film Mar 25, 2020 Abandoned
Array ( [id] => 17730837 [patent_doc_number] => 11387239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Semiconductor memory device structure [patent_app_type] => utility [patent_app_number] => 16/810572 [patent_app_country] => US [patent_app_date] => 2020-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5505 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 367 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16810572 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/810572
Semiconductor memory device structure Mar 4, 2020 Issued
Array ( [id] => 19886919 [patent_doc_number] => 12272650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Microelectronic package with substrate cavity for bridge-attach [patent_app_type] => utility [patent_app_number] => 16/804835 [patent_app_country] => US [patent_app_date] => 2020-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8705 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16804835 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/804835
Microelectronic package with substrate cavity for bridge-attach Feb 27, 2020 Issued
Array ( [id] => 16586103 [patent_doc_number] => 20210020505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/797990 [patent_app_country] => US [patent_app_date] => 2020-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9504 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16797990 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/797990
METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE Feb 20, 2020 Abandoned
Array ( [id] => 18120708 [patent_doc_number] => 11552107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 16/793543 [patent_app_country] => US [patent_app_date] => 2020-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 117 [patent_no_of_words] => 33280 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16793543 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/793543
Display device Feb 17, 2020 Issued
Array ( [id] => 18212871 [patent_doc_number] => 20230059135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => DISPLAY DEVICE RELATED TO MICRO-LED AND MANUFACTURING METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 17/784271 [patent_app_country] => US [patent_app_date] => 2020-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12146 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17784271 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/784271
DISPLAY DEVICE RELATED TO MICRO-LED AND MANUFACTURING METHOD THEREFOR Jan 30, 2020 Pending
Array ( [id] => 17551799 [patent_doc_number] => 20220123141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => SILICON CARBIDE SEMICONDUCTOR CHIP AND SILICON CARBIDE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/429513 [patent_app_country] => US [patent_app_date] => 2020-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6952 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17429513 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/429513
SILICON CARBIDE SEMICONDUCTOR CHIP AND SILICON CARBIDE SEMICONDUCTOR DEVICE Jan 28, 2020 Abandoned
Array ( [id] => 15906533 [patent_doc_number] => 20200152787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => LATERAL INSULATED-GATE BIPOLAR TRANSISTOR AND METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 16/747264 [patent_app_country] => US [patent_app_date] => 2020-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747264 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/747264
Lateral insulated-gate bipolar transistor and method therefor Jan 19, 2020 Issued
Array ( [id] => 18766916 [patent_doc_number] => 11817325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Methods of manufacturing a semiconductor package [patent_app_type] => utility [patent_app_number] => 16/746192 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9501 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746192 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/746192
Methods of manufacturing a semiconductor package Jan 16, 2020 Issued
Array ( [id] => 17224704 [patent_doc_number] => 11177214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Interconnects with hybrid metal conductors [patent_app_type] => utility [patent_app_number] => 16/743247 [patent_app_country] => US [patent_app_date] => 2020-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 6018 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16743247 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/743247
Interconnects with hybrid metal conductors Jan 14, 2020 Issued
Array ( [id] => 17284126 [patent_doc_number] => 11201168 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Semiconductor devices including flared source structures [patent_app_type] => utility [patent_app_number] => 16/735085 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 9762 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16735085 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/735085
Semiconductor devices including flared source structures Jan 5, 2020 Issued
Array ( [id] => 15807503 [patent_doc_number] => 20200126894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => INTEGRATED PASSIVE DEVICE AND FABRICATION METHOD USING A LAST THROUGH-SUBSTRATE VIA [patent_app_type] => utility [patent_app_number] => 16/722419 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6724 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16722419 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/722419
Integrated passive device and fabrication method using a last through-substrate via Dec 19, 2019 Issued
Array ( [id] => 16684518 [patent_doc_number] => 10944010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-09 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/720151 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 30 [patent_no_of_words] => 13262 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16720151 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/720151
Semiconductor device Dec 18, 2019 Issued
Array ( [id] => 15807541 [patent_doc_number] => 20200126913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => Method of Preventing Pattern Collapse [patent_app_type] => utility [patent_app_number] => 16/719626 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5064 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16719626 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/719626
Method of preventing pattern collapse Dec 17, 2019 Issued
Array ( [id] => 16904949 [patent_doc_number] => 20210183865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => SEMICONDUCTOR STRUCTURE FORMATION [patent_app_type] => utility [patent_app_number] => 16/711531 [patent_app_country] => US [patent_app_date] => 2019-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16711531 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/711531
Semiconductor structure formation at differential depths Dec 11, 2019 Issued
Array ( [id] => 18000924 [patent_doc_number] => 11502035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Interconnect structure and method of forming same [patent_app_type] => utility [patent_app_number] => 16/707450 [patent_app_country] => US [patent_app_date] => 2019-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5305 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16707450 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/707450
Interconnect structure and method of forming same Dec 8, 2019 Issued
Array ( [id] => 15746103 [patent_doc_number] => 20200111941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => DRIVING BACKPLANE, MICRO-LED DISPLAY PANEL AND DISPLAY DEVICES [patent_app_type] => utility [patent_app_number] => 16/705243 [patent_app_country] => US [patent_app_date] => 2019-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16705243 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/705243
Driving backplane, micro-LED display panel and display devices Dec 5, 2019 Issued
Array ( [id] => 16163201 [patent_doc_number] => 20200219833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/704217 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7084 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16704217 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/704217
SEMICONDUCTOR PACKAGE Dec 4, 2019 Abandoned
Array ( [id] => 17590737 [patent_doc_number] => 11329014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 16/703279 [patent_app_country] => US [patent_app_date] => 2019-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 10582 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16703279 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/703279
Semiconductor package Dec 3, 2019 Issued
Menu