Search

Phat X. Cao

Examiner (ID: 4407, Phone: (571)272-1703 , Office: P/2817 )

Most Active Art Unit
2814
Art Unit(s)
2814, 2817, 2508
Total Applications
1671
Issued Applications
1258
Pending Applications
66
Abandoned Applications
373

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18061813 [patent_doc_number] => 20220392900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => MEMORY DEVICE USING SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/884820 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10620 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 479 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884820 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884820
MEMORY DEVICE USING SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING THE SAME Aug 9, 2022 Abandoned
Array ( [id] => 18195109 [patent_doc_number] => 20230048628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => INPUT/OUTPUT CONNECTIONS OF WAFER-ON-WAFER BONDED MEMORY AND LOGIC [patent_app_type] => utility [patent_app_number] => 17/885269 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12452 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17885269 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/885269
Input/output connections of wafer-on-wafer bonded memory and logic Aug 9, 2022 Issued
Array ( [id] => 18823081 [patent_doc_number] => 20230397422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => MERGED CAVITIES AND BURIED ETCH STOPS FOR THREE-DIMENSIONAL MEMORY ARRAYS [patent_app_type] => utility [patent_app_number] => 17/884299 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884299 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884299
Merged cavities and buried etch stops for three-dimensional memory arrays Aug 8, 2022 Issued
Array ( [id] => 18008698 [patent_doc_number] => 20220367465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => Integrated Memory Comprising Secondary Access Devices Between Digit Lines and Primary Access Devices [patent_app_type] => utility [patent_app_number] => 17/877628 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17877628 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/877628
Integrated memory comprising secondary access devices between digit lines and primary access devices Jul 28, 2022 Issued
Array ( [id] => 18652800 [patent_doc_number] => 20230298640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => SYSTEMS AND METHODS FOR RESOLVING DATA (DQ) LINE SWAPPING CONFIGURATIONS IN DOUBLE DATA RATE (DDR) MEMORIES [patent_app_type] => utility [patent_app_number] => 17/815599 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4417 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815599 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815599
Systems and methods for resolving data (DQ) line swapping configurations in double data rate (DDR) memories Jul 27, 2022 Issued
Array ( [id] => 18022863 [patent_doc_number] => 20220374362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE [patent_app_type] => utility [patent_app_number] => 17/875572 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 95329 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17875572 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/875572
Methods and apparatus to facilitate atomic operations in victim cache Jul 27, 2022 Issued
Array ( [id] => 19062902 [patent_doc_number] => 11942147 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Semiconducting metal oxide memory device using hydrogen-mediated threshold voltage modulation and methods for forming the same [patent_app_type] => utility [patent_app_number] => 17/872111 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 30 [patent_no_of_words] => 15178 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872111 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/872111
Semiconducting metal oxide memory device using hydrogen-mediated threshold voltage modulation and methods for forming the same Jul 24, 2022 Issued
Array ( [id] => 18840298 [patent_doc_number] => 11848381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Methods of operating multi-bit memory storage device [patent_app_type] => utility [patent_app_number] => 17/871315 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 12906 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871315 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/871315
Methods of operating multi-bit memory storage device Jul 21, 2022 Issued
Array ( [id] => 19314204 [patent_doc_number] => 12040028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Low voltage one-time-programmable memory and array thereof [patent_app_type] => utility [patent_app_number] => 17/813046 [patent_app_country] => US [patent_app_date] => 2022-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3012 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813046 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/813046
Low voltage one-time-programmable memory and array thereof Jul 17, 2022 Issued
Array ( [id] => 18113036 [patent_doc_number] => 20230005916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => THIN FILM TRANSISTOR DECK SELECTION IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/863970 [patent_app_country] => US [patent_app_date] => 2022-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24263 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17863970 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/863970
Thin film transistor deck selection in a memory device Jul 12, 2022 Issued
Array ( [id] => 17985731 [patent_doc_number] => 20220351768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => FERROELECTRIC DEVICES AND FERROELECTRIC MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/812132 [patent_app_country] => US [patent_app_date] => 2022-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7370 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17812132 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/812132
Ferroelectric devices and ferroelectric memory cells Jul 11, 2022 Issued
Array ( [id] => 18170073 [patent_doc_number] => 20230036684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => BIT LINE SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/859153 [patent_app_country] => US [patent_app_date] => 2022-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7589 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17859153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/859153
Bit line sense amplifier and semiconductor memory apparatus using the same Jul 6, 2022 Issued
Array ( [id] => 19494097 [patent_doc_number] => 12112818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Scan chain compression for testing memory of a system on a chip [patent_app_type] => utility [patent_app_number] => 17/856744 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856744 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/856744
Scan chain compression for testing memory of a system on a chip Jun 30, 2022 Issued
Array ( [id] => 17949011 [patent_doc_number] => 20220336030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => Multi-Fuse Memory Cell Circuit and Method [patent_app_type] => utility [patent_app_number] => 17/855876 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17855876 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/855876
Multi-fuse memory cell circuit and method Jun 30, 2022 Issued
Array ( [id] => 18442214 [patent_doc_number] => 20230189510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/854130 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854130 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854130
SEMICONDUCTOR DEVICE Jun 29, 2022 Issued
Array ( [id] => 18377943 [patent_doc_number] => 20230153030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => STORAGE DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/810067 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6969 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17810067 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/810067
Storage device and operating method thereof Jun 29, 2022 Issued
Array ( [id] => 18585723 [patent_doc_number] => 20230267987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => METHOD AND APPARATUS FOR INTENSIFYING CURRENT LEAKAGE BETWEEN ADJACENT MEMORY CELLS, AND METHOD AND APPARATUS FOR CURRENT LEAKAGE DETECTION [patent_app_type] => utility [patent_app_number] => 17/809551 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6278 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17809551 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/809551
Method and apparatus for intensifying current leakage between adjacent memory cells, and method and apparatus for current leakage detection Jun 27, 2022 Issued
Array ( [id] => 17932966 [patent_doc_number] => 20220328092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => MEMORY DEVICE AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/849894 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 40341 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17849894 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/849894
Memory device and electronic device Jun 26, 2022 Issued
Array ( [id] => 19626871 [patent_doc_number] => 12165718 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Memory device and method of operating the same [patent_app_type] => utility [patent_app_number] => 17/849247 [patent_app_country] => US [patent_app_date] => 2022-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 13614 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17849247 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/849247
Memory device and method of operating the same Jun 23, 2022 Issued
Array ( [id] => 18423657 [patent_doc_number] => 20230178121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => HIGH-BANDWIDTH MEMORY MODULE ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/849089 [patent_app_country] => US [patent_app_date] => 2022-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7740 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17849089 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/849089
High-bandwidth memory module architecture Jun 23, 2022 Issued
Menu