Search

Phat X. Cao

Examiner (ID: 4407, Phone: (571)272-1703 , Office: P/2817 )

Most Active Art Unit
2814
Art Unit(s)
2814, 2817, 2508
Total Applications
1671
Issued Applications
1258
Pending Applications
66
Abandoned Applications
373

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18774021 [patent_doc_number] => 20230368851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => POST-WRITE READ TECHNIQUES TO IMPROVE PROGRAMMING RELIABILITY IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/741182 [patent_app_country] => US [patent_app_date] => 2022-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741182 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/741182
Post-write read techniques to improve programming reliability in a memory device May 9, 2022 Issued
Array ( [id] => 17810590 [patent_doc_number] => 20220262425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => VERTICAL MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/739944 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19389 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17739944 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/739944
Vertical memory device May 8, 2022 Issued
Array ( [id] => 17810965 [patent_doc_number] => 20220262800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => Dual-Port Semiconductor Memory and First In First Out (FIFO) Memory Having Electrically Floating Body Transistor [patent_app_type] => utility [patent_app_number] => 17/737295 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29826 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737295 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/737295
Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor May 4, 2022 Issued
Array ( [id] => 18307157 [patent_doc_number] => 20230111057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => MAGNETIC TUNNEL JUNCTION DEVICE AND STOCHASTIC COMPUTING SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/734455 [patent_app_country] => US [patent_app_date] => 2022-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17734455 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/734455
MAGNETIC TUNNEL JUNCTION DEVICE AND STOCHASTIC COMPUTING SYSTEM INCLUDING THE SAME May 1, 2022 Pending
Array ( [id] => 18950777 [patent_doc_number] => 11894080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Time-tagging read levels of multiple wordlines for open block data retention [patent_app_type] => utility [patent_app_number] => 17/733042 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 13524 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17733042 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/733042
Time-tagging read levels of multiple wordlines for open block data retention Apr 28, 2022 Issued
Array ( [id] => 17795691 [patent_doc_number] => 20220254783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/731611 [patent_app_country] => US [patent_app_date] => 2022-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6597 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17731611 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/731611
Semiconductor memory device Apr 27, 2022 Issued
Array ( [id] => 19110167 [patent_doc_number] => 11963299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Load reduced memory module [patent_app_type] => utility [patent_app_number] => 17/726354 [patent_app_country] => US [patent_app_date] => 2022-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 14277 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17726354 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/726354
Load reduced memory module Apr 20, 2022 Issued
Array ( [id] => 18679505 [patent_doc_number] => 20230317161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => MATRIX MULTIPLICATION WITH RESISTIVE MEMORY CIRCUIT HAVING GOOD SUBSTRATE DENSITY [patent_app_type] => utility [patent_app_number] => 17/710851 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17710851 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/710851
MATRIX MULTIPLICATION WITH RESISTIVE MEMORY CIRCUIT HAVING GOOD SUBSTRATE DENSITY Mar 30, 2022 Abandoned
Array ( [id] => 19523788 [patent_doc_number] => 12125526 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Memory with bitcell power boosting [patent_app_type] => utility [patent_app_number] => 17/657231 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6155 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17657231 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/657231
Memory with bitcell power boosting Mar 29, 2022 Issued
Array ( [id] => 17948981 [patent_doc_number] => 20220336000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => MEMORY DEVICE GENERATING OPTIMAL WRITE VOLTAGE BASED ON SIZE OF MEMORY CELL AND INITIAL WRITE VOLTAGE [patent_app_type] => utility [patent_app_number] => 17/707027 [patent_app_country] => US [patent_app_date] => 2022-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12355 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17707027 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/707027
Memory device generating optimal write voltage based on size of memory cell and initial write voltage Mar 28, 2022 Issued
Array ( [id] => 17723594 [patent_doc_number] => 20220216316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => METHOD OF MAKING SPLIT-GATE NON-VOLATILE MEMORY CELLS WITH ERASE GATES DISPOSED OVER WORD LINE GATES [patent_app_type] => utility [patent_app_number] => 17/701840 [patent_app_country] => US [patent_app_date] => 2022-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4846 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 461 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701840 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/701840
Method of making split-gate non-volatile memory cells with erase gates disposed over word line gates Mar 22, 2022 Issued
Array ( [id] => 17708252 [patent_doc_number] => 20220208260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => MULTINARY BIT CELLS FOR MEMORY DEVICES AND NETWORK APPLICATIONS AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/699253 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10641 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699253 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/699253
Multinary bit cells for memory devices and network applications and method of manufacturing the same Mar 20, 2022 Issued
Array ( [id] => 18652806 [patent_doc_number] => 20230298646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => DETERMINISTIC VOLTAGE-CONTROLLED MAGNETIC ANISOTROPY (VCMA) MRAM WITH SPIN-TRANSFER TORQUE (STT) MRAM ASSISTANCE [patent_app_type] => utility [patent_app_number] => 17/655569 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6808 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17655569 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/655569
DETERMINISTIC VOLTAGE-CONTROLLED MAGNETIC ANISOTROPY (VCMA) MRAM WITH SPIN-TRANSFER TORQUE (STT) MRAM ASSISTANCE Mar 20, 2022 Pending
Array ( [id] => 18528514 [patent_doc_number] => 11715512 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Apparatuses and methods for dynamic targeted refresh steals [patent_app_type] => utility [patent_app_number] => 17/654035 [patent_app_country] => US [patent_app_date] => 2022-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11071 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654035 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654035
Apparatuses and methods for dynamic targeted refresh steals Mar 7, 2022 Issued
Array ( [id] => 17763383 [patent_doc_number] => 20220236995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => APPARATUSES AND METHODS FOR ORDERING BITS IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/680538 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17680538 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/680538
Apparatuses and methods for ordering bits in a memory device Feb 24, 2022 Issued
Array ( [id] => 17660481 [patent_doc_number] => 20220180946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => MEMORY CONTROLLER AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/681401 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17681401 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/681401
Memory controller and operating method thereof Feb 24, 2022 Issued
Array ( [id] => 19416547 [patent_doc_number] => 12082409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells [patent_app_type] => utility [patent_app_number] => 17/674289 [patent_app_country] => US [patent_app_date] => 2022-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 36 [patent_no_of_words] => 6400 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17674289 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/674289
Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells Feb 16, 2022 Issued
Array ( [id] => 18761545 [patent_doc_number] => 11812599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Compute near memory with backend memory [patent_app_type] => utility [patent_app_number] => 17/670248 [patent_app_country] => US [patent_app_date] => 2022-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 14572 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17670248 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/670248
Compute near memory with backend memory Feb 10, 2022 Issued
Array ( [id] => 17900504 [patent_doc_number] => 20220310166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => IN-LINE PROGRAMMING ADJUSTMENT OF A MEMORY CELL IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/670037 [patent_app_country] => US [patent_app_date] => 2022-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17670037 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/670037
In-line programming adjustment of a memory cell in a memory sub-system Feb 10, 2022 Issued
Array ( [id] => 18912880 [patent_doc_number] => 11875865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Select gate reliability [patent_app_type] => utility [patent_app_number] => 17/670111 [patent_app_country] => US [patent_app_date] => 2022-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9223 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17670111 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/670111
Select gate reliability Feb 10, 2022 Issued
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