Search

Phat X. Cao

Examiner (ID: 4407, Phone: (571)272-1703 , Office: P/2817 )

Most Active Art Unit
2814
Art Unit(s)
2814, 2817, 2508
Total Applications
1671
Issued Applications
1258
Pending Applications
66
Abandoned Applications
373

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18138912 [patent_doc_number] => 20230012747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => COMPILATION METHOD, COMPILATION CIRCUIT, MODE REGISTER, AND MEMORY [patent_app_type] => utility [patent_app_number] => 17/650543 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9676 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17650543 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/650543
Compilation method, compilation circuit, mode register, and memory Feb 9, 2022 Issued
Array ( [id] => 18998923 [patent_doc_number] => 11915777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Integrated assemblies and methods forming integrated assemblies [patent_app_type] => utility [patent_app_number] => 17/669189 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4963 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17669189 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/669189
Integrated assemblies and methods forming integrated assemblies Feb 9, 2022 Issued
Array ( [id] => 18555008 [patent_doc_number] => 20230253024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => TECHNIQUES FOR MEMORY SYSTEM REFRESH [patent_app_type] => utility [patent_app_number] => 17/668197 [patent_app_country] => US [patent_app_date] => 2022-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17668197 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/668197
Techniques for memory system refresh Feb 8, 2022 Issued
Array ( [id] => 19123356 [patent_doc_number] => 11967350 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-04-23 [patent_title] => System and method for current controlled nanowire memory device [patent_app_type] => utility [patent_app_number] => 17/589739 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4220 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17589739 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/589739
System and method for current controlled nanowire memory device Jan 30, 2022 Issued
Array ( [id] => 17615106 [patent_doc_number] => 20220157386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => SECURE ERASE FOR DATA CORRUPTION [patent_app_type] => utility [patent_app_number] => 17/589172 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12597 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17589172 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/589172
Secure erase for data corruption Jan 30, 2022 Issued
Array ( [id] => 18464152 [patent_doc_number] => 11688445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Valley spin hall effect based non-volatile memory [patent_app_type] => utility [patent_app_number] => 17/588317 [patent_app_country] => US [patent_app_date] => 2022-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 33 [patent_no_of_words] => 7681 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588317 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/588317
Valley spin hall effect based non-volatile memory Jan 29, 2022 Issued
Array ( [id] => 18532972 [patent_doc_number] => 20230238047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => MEMORY UNIT WITH TIME DOMAIN EDGE DELAY ACCUMULATION FOR COMPUTING-IN-MEMORY APPLICATIONS AND COMPUTING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/580651 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580651 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/580651
Memory unit with time domain edge delay accumulation for computing-in-memory applications and computing method thereof Jan 20, 2022 Issued
Array ( [id] => 17582616 [patent_doc_number] => 20220139471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTIVALUED DATA [patent_app_type] => utility [patent_app_number] => 17/578956 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28744 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 529 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578956 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/578956
SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTIVALUED DATA Jan 18, 2022 Abandoned
Array ( [id] => 19108461 [patent_doc_number] => 11961574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Memory device and method of operating the same [patent_app_type] => utility [patent_app_number] => 17/575393 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 12023 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17575393 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/575393
Memory device and method of operating the same Jan 12, 2022 Issued
Array ( [id] => 17582612 [patent_doc_number] => 20220139467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 17/575554 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25358 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17575554 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/575554
Semiconductor memory Jan 12, 2022 Issued
Array ( [id] => 18292157 [patent_doc_number] => 11621030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-04 [patent_title] => Protocol for memory power-mode control [patent_app_type] => utility [patent_app_number] => 17/568656 [patent_app_country] => US [patent_app_date] => 2022-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4536 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568656 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/568656
Protocol for memory power-mode control Jan 3, 2022 Issued
Array ( [id] => 18607891 [patent_doc_number] => 11749367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Circuit and method for capturing and transporting data errors [patent_app_type] => utility [patent_app_number] => 17/567481 [patent_app_country] => US [patent_app_date] => 2022-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 8572 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17567481 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/567481
Circuit and method for capturing and transporting data errors Jan 2, 2022 Issued
Array ( [id] => 18377753 [patent_doc_number] => 20230152840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => REGISTER CLOCK DRIVER WITH CHIP SELECT LOOPBACK [patent_app_type] => utility [patent_app_number] => 17/566926 [patent_app_country] => US [patent_app_date] => 2021-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17566926 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/566926
Register clock driver with chip select loopback Dec 30, 2021 Issued
Array ( [id] => 18623570 [patent_doc_number] => 11756623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Semiconductor storage device [patent_app_type] => utility [patent_app_number] => 17/565241 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 13715 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17565241 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/565241
Semiconductor storage device Dec 28, 2021 Issued
Array ( [id] => 18688149 [patent_doc_number] => 11783892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/559891 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 10331 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559891 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559891
Semiconductor memory device Dec 21, 2021 Issued
Array ( [id] => 20345803 [patent_doc_number] => 12469538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Resistance change memory, memory device, and memory system [patent_app_type] => utility [patent_app_number] => 18/258405 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 4652 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18258405 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/258405
Resistance change memory, memory device, and memory system Dec 15, 2021 Issued
Array ( [id] => 17992956 [patent_doc_number] => 20220358993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => MEMORY CIRCUITS, MEMORY STRUCTURES, AND METHODS FOR FABRICATING A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/643191 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9259 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17643191 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/643191
Memory circuits, memory structures, and methods for fabricating a memory device Dec 7, 2021 Issued
Array ( [id] => 19092883 [patent_doc_number] => 11954338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Shared components in fuse match logic [patent_app_type] => utility [patent_app_number] => 17/544407 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6524 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17544407 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/544407
Shared components in fuse match logic Dec 6, 2021 Issued
Array ( [id] => 18426002 [patent_doc_number] => 20230180467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => VERTICAL ACCESS LINE IN A FOLDED DIGITLINE SENSE AMPLIFIER [patent_app_type] => utility [patent_app_number] => 17/540589 [patent_app_country] => US [patent_app_date] => 2021-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5217 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17540589 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/540589
Vertical access line in a folded digitline sense amplifier Dec 1, 2021 Issued
Array ( [id] => 18839969 [patent_doc_number] => 11848048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Memory device decoder configurations [patent_app_type] => utility [patent_app_number] => 17/456968 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 17459 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456968 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/456968
Memory device decoder configurations Nov 29, 2021 Issued
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