Search

Phat X. Cao

Examiner (ID: 7067)

Most Active Art Unit
2814
Art Unit(s)
2508, 2817, 2814
Total Applications
1687
Issued Applications
1251
Pending Applications
92
Abandoned Applications
373

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15462381 [patent_doc_number] => 20200044015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => EPITAXIAL STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/452558 [patent_app_country] => US [patent_app_date] => 2019-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16452558 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/452558
Epitaxial structure Jun 25, 2019 Issued
Array ( [id] => 15370017 [patent_doc_number] => 20200020773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/452668 [patent_app_country] => US [patent_app_date] => 2019-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16452668 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/452668
Semiconductor device having increased contact area between a source/drain pattern and an active contact Jun 25, 2019 Issued
Array ( [id] => 14969015 [patent_doc_number] => 20190311986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => FORMING DUAL METALLIZATION INTERCONNECT STRUCTURES IN SINGLE METALLIZATION LEVEL [patent_app_type] => utility [patent_app_number] => 16/445428 [patent_app_country] => US [patent_app_date] => 2019-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16445428 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/445428
Forming dual metallization interconnect structures in single metallization level Jun 18, 2019 Issued
Array ( [id] => 16515981 [patent_doc_number] => 20200395239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => LINE STRUCTURE FOR FAN-OUT CIRCUIT AND MANUFACTURING METHOD THEREOF, AND PHOTOMASK PATTERN FOR FAN-OUT CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/439499 [patent_app_country] => US [patent_app_date] => 2019-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16439499 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/439499
Line structure for fan-out circuit and manufacturing method thereof, and photomask pattern for fan-out circuit Jun 11, 2019 Issued
Array ( [id] => 14843583 [patent_doc_number] => 20190280192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => Multiferroic Magnetic Tunnel Junction Devices [patent_app_type] => utility [patent_app_number] => 16/414537 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3376 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414537 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/414537
Multiferroic magnetic tunnel junction devices May 15, 2019 Issued
Array ( [id] => 16479655 [patent_doc_number] => 10854611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Memory cells and memory arrays [patent_app_type] => utility [patent_app_number] => 16/412750 [patent_app_country] => US [patent_app_date] => 2019-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5079 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16412750 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/412750
Memory cells and memory arrays May 14, 2019 Issued
Array ( [id] => 16464281 [patent_doc_number] => 10847644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Gallium nitride transistor with improved termination structure [patent_app_type] => utility [patent_app_number] => 16/391731 [patent_app_country] => US [patent_app_date] => 2019-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 7000 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16391731 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/391731
Gallium nitride transistor with improved termination structure Apr 22, 2019 Issued
Array ( [id] => 14676869 [patent_doc_number] => 20190237549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => SEMICONDUCTOR DEVICE WITH A WELL REGION [patent_app_type] => utility [patent_app_number] => 16/374893 [patent_app_country] => US [patent_app_date] => 2019-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8302 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16374893 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/374893
Semiconductor device with a well region Apr 3, 2019 Issued
Array ( [id] => 14587821 [patent_doc_number] => 20190221519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => FORMING DUAL METALLIZATION INTERCONNECT STRUCTURES IN SINGLE METALLIZATION LEVEL [patent_app_type] => utility [patent_app_number] => 16/364700 [patent_app_country] => US [patent_app_date] => 2019-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6058 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16364700 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/364700
Forming dual metallization interconnect structures in single metallization level Mar 25, 2019 Issued
Array ( [id] => 15657615 [patent_doc_number] => 20200091338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/298210 [patent_app_country] => US [patent_app_date] => 2019-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16298210 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/298210
Semiconductor device with reduced electric field crowding Mar 10, 2019 Issued
Array ( [id] => 16316170 [patent_doc_number] => 20200294908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => BONDED STRUCTURES WITH INTEGRATED PASSIVE COMPONENT [patent_app_type] => utility [patent_app_number] => 16/298466 [patent_app_country] => US [patent_app_date] => 2019-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16298466 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/298466
Bonded structures with integrated passive component Mar 10, 2019 Issued
Array ( [id] => 14938971 [patent_doc_number] => 20190305124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/298068 [patent_app_country] => US [patent_app_date] => 2019-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5578 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16298068 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/298068
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE Mar 10, 2019 Abandoned
Array ( [id] => 15688225 [patent_doc_number] => 20200098776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/298078 [patent_app_country] => US [patent_app_date] => 2019-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16298078 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/298078
Semiconductor memory device Mar 10, 2019 Issued
Array ( [id] => 16316279 [patent_doc_number] => 20200295017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => MULTI-LEVEL FERROELECTRIC MEMORY CELL [patent_app_type] => utility [patent_app_number] => 16/298413 [patent_app_country] => US [patent_app_date] => 2019-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16298413 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/298413
Multi-level ferroelectric memory cell Mar 10, 2019 Issued
Array ( [id] => 15657101 [patent_doc_number] => 20200091081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/298056 [patent_app_country] => US [patent_app_date] => 2019-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2219 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16298056 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/298056
Semiconductor device having a stack body including metal films and first insulating films alternately stacked on a semiconductor substrate and including a stepped end portion and manufacturing method thereof Mar 10, 2019 Issued
Array ( [id] => 15598053 [patent_doc_number] => 20200075561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/298421 [patent_app_country] => US [patent_app_date] => 2019-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6932 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16298421 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/298421
SEMICONDUCTOR PACKAGE Mar 10, 2019 Abandoned
Array ( [id] => 16410075 [patent_doc_number] => 10818639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => 3D stack of electronic chips [patent_app_type] => utility [patent_app_number] => 16/298414 [patent_app_country] => US [patent_app_date] => 2019-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7022 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16298414 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/298414
3D stack of electronic chips Mar 10, 2019 Issued
Array ( [id] => 16048357 [patent_doc_number] => 10686064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Nitride semiconductor device and fabrication method therefor [patent_app_type] => utility [patent_app_number] => 16/295777 [patent_app_country] => US [patent_app_date] => 2019-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 39 [patent_no_of_words] => 21406 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16295777 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/295777
Nitride semiconductor device and fabrication method therefor Mar 6, 2019 Issued
Array ( [id] => 14509723 [patent_doc_number] => 20190198516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => MEMORY HAVING A CONTINUOUS CHANNEL [patent_app_type] => utility [patent_app_number] => 16/291453 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291453 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/291453
Memory having a continuous channel Mar 3, 2019 Issued
Array ( [id] => 14446739 [patent_doc_number] => 20190181243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => DUAL-CURVATURE CAVITY FOR EPITAXIAL SEMICONDUCTOR GROWTH [patent_app_type] => utility [patent_app_number] => 16/276045 [patent_app_country] => US [patent_app_date] => 2019-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16276045 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/276045
DUAL-CURVATURE CAVITY FOR EPITAXIAL SEMICONDUCTOR GROWTH Feb 13, 2019 Abandoned
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