Phat X. Cao

Array ( [id] => 17477107 [patent_doc_number] => 20220084611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => ONE-TIME-PROGRAMMABLE MEMORY [patent_app_type] => utility [patent_app_number] => 17/536639 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17536639 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19305230 [patent_doc_number] => 20240233810 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => STORAGE DEVICE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC DEVICE INCLUDING STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/548035 [patent_app_country] => US [patent_app_date] => 2021-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8733 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18548035 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19305230 [patent_doc_number] => 20240233810 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => STORAGE DEVICE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC DEVICE INCLUDING STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/548035 [patent_app_country] => US [patent_app_date] => 2021-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8733 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18548035 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18396935 [patent_doc_number] => 20230165156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM) WITH PRESERVED UNDERLYING DIELECTRIC LAYER [patent_app_type] => utility [patent_app_number] => 17/534485 [patent_app_country] => US [patent_app_date] => 2021-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6508 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17534485 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18704456 [patent_doc_number] => 11790972 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-17 [patent_title] => Writing scheme for multi-element gain ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches and control on the plate-lines of the bit-cell [patent_app_type] => utility [patent_app_number] => 17/532652 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54502 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532652 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18578706 [patent_doc_number] => 11735245 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-08-22 [patent_title] => Read scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects [patent_app_type] => utility [patent_app_number] => 17/532552 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54496 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18480986 [patent_doc_number] => 11694737 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-07-04 [patent_title] => Write scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to word-line to minimize write disturb effects [patent_app_type] => utility [patent_app_number] => 17/532545 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54399 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532545 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18645465 [patent_doc_number] => 11769543 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-26 [patent_title] => Writing scheme for 1TNC ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches and control on the plate-lines of the bit-cell [patent_app_type] => utility [patent_app_number] => 17/532556 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54495 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532556 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18766733 [patent_doc_number] => 11817140 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-11-14 [patent_title] => Reading scheme for 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line and with individual switches and control on plate-lines of the bit-cell [patent_app_type] => utility [patent_app_number] => 17/532647 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54505 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18357665 [patent_doc_number] => 11646071 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-05-09 [patent_title] => Reading scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to bit-line and with individual switches and control on plate-lines of the bit-cell [patent_app_type] => utility [patent_app_number] => 17/532657 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18248817 [patent_doc_number] => 11605413 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-03-14 [patent_title] => Reading scheme for multi-element gain ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell [patent_app_type] => utility [patent_app_number] => 17/531577 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54519 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531577 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18401916 [patent_doc_number] => 11664060 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-05-30 [patent_title] => Writing scheme for multi-element gain ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell [patent_app_type] => utility [patent_app_number] => 17/531535 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531535 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18507384 [patent_doc_number] => 11705208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Read level calibration in memory devices using embedded servo cells [patent_app_type] => utility [patent_app_number] => 17/530368 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6438 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530368 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18073507 [patent_doc_number] => 11532344 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-20 [patent_title] => Reading scheme for 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line and with individual switches on plate-lines of the bit-cell [patent_app_type] => utility [patent_app_number] => 17/530366 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530366 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18088375 [patent_doc_number] => 11538514 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-27 [patent_title] => Writing scheme for 1TnC ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell [patent_app_type] => utility [patent_app_number] => 17/530364 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54499 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530364 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18047710 [patent_doc_number] => 11521668 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-06 [patent_title] => Pulsing scheme for a ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects [patent_app_type] => utility [patent_app_number] => 17/530360 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54507 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530360 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17463463 [patent_doc_number] => 20220076769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => STACKED SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/530291 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9050 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18262913 [patent_doc_number] => 11610620 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-03-21 [patent_title] => Pulsing scheme for a 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line to minimize read or write disturb effects [patent_app_type] => utility [patent_app_number] => 17/530362 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54521 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530362 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18262912 [patent_doc_number] => 11610619 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-03-21 [patent_title] => Pulsing scheme for a 1TNC ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects [patent_app_type] => utility [patent_app_number] => 17/530363 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54508 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530363 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17956157 [patent_doc_number] => 11482270 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-25 [patent_title] => Pulsing scheme for a ferroelectric memory bit-cell to minimize read or write disturb effect and refresh logic [patent_app_type] => utility [patent_app_number] => 17/529258 [patent_app_country] => US [patent_app_date] => 2021-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 54437 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529258 [rel_patent_id] =>[rel_patent_doc_number] =>)