Search

Phat X. Cao

Examiner (ID: 7067)

Most Active Art Unit
2814
Art Unit(s)
2508, 2817, 2814
Total Applications
1687
Issued Applications
1251
Pending Applications
92
Abandoned Applications
373

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16132429 [patent_doc_number] => 10699982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-30 [patent_title] => Semiconductor package and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/272484 [patent_app_country] => US [patent_app_date] => 2019-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4306 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16272484 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/272484
Semiconductor package and method of manufacturing the same Feb 10, 2019 Issued
Array ( [id] => 17381354 [patent_doc_number] => 11239387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Light emitting diode with high efficiency [patent_app_type] => utility [patent_app_number] => 16/246192 [patent_app_country] => US [patent_app_date] => 2019-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 20604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16246192 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/246192
Light emitting diode with high efficiency Jan 10, 2019 Issued
Array ( [id] => 15315533 [patent_doc_number] => 10522482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Semiconductor device manufacturing method comprising bonding an electrode terminal to a conductive pattern on an insulating substrate using ultrasonic bonding [patent_app_type] => utility [patent_app_number] => 16/237311 [patent_app_country] => US [patent_app_date] => 2018-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 9148 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16237311 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/237311
Semiconductor device manufacturing method comprising bonding an electrode terminal to a conductive pattern on an insulating substrate using ultrasonic bonding Dec 30, 2018 Issued
Array ( [id] => 14191685 [patent_doc_number] => 20190115548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => PHOTO-PATTERNABLE GATE DIELECTRICS FOR OFET [patent_app_type] => utility [patent_app_number] => 16/223645 [patent_app_country] => US [patent_app_date] => 2018-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9507 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16223645 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/223645
Photo-patternable gate dielectrics for OFET Dec 17, 2018 Issued
Array ( [id] => 14476435 [patent_doc_number] => 20190189866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/216882 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16216882 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/216882
Light emitting element including adhesive member containing particles Dec 10, 2018 Issued
Array ( [id] => 13996303 [patent_doc_number] => 20190067309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => Method for Forming a PN Junction and Associated Semiconductor Device [patent_app_type] => utility [patent_app_number] => 16/175030 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175030 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/175030
Method for Forming a PN Junction and Associated Semiconductor Device Oct 29, 2018 Abandoned
Array ( [id] => 13996303 [patent_doc_number] => 20190067309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => Method for Forming a PN Junction and Associated Semiconductor Device [patent_app_type] => utility [patent_app_number] => 16/175030 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175030 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/175030
Method for Forming a PN Junction and Associated Semiconductor Device Oct 29, 2018 Abandoned
Array ( [id] => 15428079 [patent_doc_number] => 10546979 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Display device and lighting apparatus [patent_app_type] => utility [patent_app_number] => 16/171354 [patent_app_country] => US [patent_app_date] => 2018-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10151 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16171354 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/171354
Display device and lighting apparatus Oct 24, 2018 Issued
Array ( [id] => 16339220 [patent_doc_number] => 10790189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => 3D integrated circuit and methods of forming the same [patent_app_type] => utility [patent_app_number] => 16/149972 [patent_app_country] => US [patent_app_date] => 2018-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4083 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16149972 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/149972
3D integrated circuit and methods of forming the same Oct 1, 2018 Issued
Array ( [id] => 16660686 [patent_doc_number] => 20210057323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => GROOVE DESIGN TO FACILITATE FLOW OF A MATERIAL BETWEEN TWO SUBSTRATES [patent_app_type] => utility [patent_app_number] => 17/052908 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6085 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17052908 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/052908
GROOVE DESIGN TO FACILITATE FLOW OF A MATERIAL BETWEEN TWO SUBSTRATES Sep 27, 2018 Abandoned
Array ( [id] => 14191539 [patent_doc_number] => 20190115475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => PROCESS TO REDUCE PLASMA INDUCED DAMAGE [patent_app_type] => utility [patent_app_number] => 16/143786 [patent_app_country] => US [patent_app_date] => 2018-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4886 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16143786 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/143786
Process to reduce plasma induced damage Sep 26, 2018 Issued
Array ( [id] => 16035335 [patent_doc_number] => 10680102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Reduction of top source/drain external resistance and parasitic capacitance in vertical transistors [patent_app_type] => utility [patent_app_number] => 16/144196 [patent_app_country] => US [patent_app_date] => 2018-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 7221 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16144196 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/144196
Reduction of top source/drain external resistance and parasitic capacitance in vertical transistors Sep 26, 2018 Issued
Array ( [id] => 13785765 [patent_doc_number] => 20190006421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => METHOD FOR FABRICATING A PHASE-CHANGE MEMORY CELL [patent_app_type] => utility [patent_app_number] => 16/113631 [patent_app_country] => US [patent_app_date] => 2018-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4905 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16113631 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/113631
METHOD FOR FABRICATING A PHASE-CHANGE MEMORY CELL Aug 26, 2018 Abandoned
Array ( [id] => 13582101 [patent_doc_number] => 20180342599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => Metal Gate Formation Through Etch Back Process [patent_app_type] => utility [patent_app_number] => 16/055399 [patent_app_country] => US [patent_app_date] => 2018-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16055399 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/055399
Metal gate formation through etch back process Aug 5, 2018 Issued
Array ( [id] => 13571397 [patent_doc_number] => 20180337246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => Method for Fabricating Metal Gate Devices and Resulting Structures [patent_app_type] => utility [patent_app_number] => 16/050687 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4966 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16050687 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/050687
Method for fabricating metal gate devices and resulting structures Jul 30, 2018 Issued
Array ( [id] => 13740709 [patent_doc_number] => 20180374824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => Semiconductor Packages with Thermal-Electrical-Mechanical Chips and Methods of Forming the Same [patent_app_type] => utility [patent_app_number] => 16/051311 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16051311 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/051311
Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same Jul 30, 2018 Issued
Array ( [id] => 15415019 [patent_doc_number] => 20200027832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => DEVICE STRUCTURE AND TECHNIQUES FOR FORMING SEMICONDUCTOR DEVICE HAVING ANGLED CONDUCTORS [patent_app_type] => utility [patent_app_number] => 16/037906 [patent_app_country] => US [patent_app_date] => 2018-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16037906 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/037906
DEVICE STRUCTURE AND TECHNIQUES FOR FORMING SEMICONDUCTOR DEVICE HAVING ANGLED CONDUCTORS Jul 16, 2018 Abandoned
Array ( [id] => 14509969 [patent_doc_number] => 20190198639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/037922 [patent_app_country] => US [patent_app_date] => 2018-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16037922 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/037922
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME Jul 16, 2018 Abandoned
Array ( [id] => 13832837 [patent_doc_number] => 20190019903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => SILICON WAVEGUIDE INTEGRATED WITH SILICON-GERMANIUM (Si-Ge) AVALANCHE PHOTODIODE DETECTOR [patent_app_type] => utility [patent_app_number] => 16/036824 [patent_app_country] => US [patent_app_date] => 2018-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16036824 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/036824
SILICON WAVEGUIDE INTEGRATED WITH SILICON-GERMANIUM (Si-Ge) AVALANCHE PHOTODIODE DETECTOR Jul 15, 2018 Abandoned
Array ( [id] => 14429821 [patent_doc_number] => 10319724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Memory cells and memory arrays [patent_app_type] => utility [patent_app_number] => 16/033377 [patent_app_country] => US [patent_app_date] => 2018-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5053 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16033377 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/033377
Memory cells and memory arrays Jul 11, 2018 Issued
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