Search

Phat X. Cao

Examiner (ID: 7067)

Most Active Art Unit
2814
Art Unit(s)
2508, 2817, 2814
Total Applications
1687
Issued Applications
1251
Pending Applications
92
Abandoned Applications
373

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16256809 [patent_doc_number] => 20200266184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => PATCH ACCOMODATING EMBEDDED DIES HAVING DIFFERENT THICKNESSES [patent_app_type] => utility [patent_app_number] => 16/649923 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16649923 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/649923
Patch accommodating embedded dies having different thicknesses Dec 28, 2017 Issued
Array ( [id] => 13499727 [patent_doc_number] => 20180301406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/854911 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15854911 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/854911
SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME Dec 26, 2017 Abandoned
Array ( [id] => 12896461 [patent_doc_number] => 20180190662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => BIT LINE GATE STRUCTURE OF DYNAMIC RANDOM ACCESS MEMORY (DRAM) AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/854825 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2402 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15854825 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/854825
BIT LINE GATE STRUCTURE OF DYNAMIC RANDOM ACCESS MEMORY (DRAM) AND FORMING METHOD THEREOF Dec 26, 2017 Abandoned
Array ( [id] => 12896788 [patent_doc_number] => 20180190771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/854769 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2972 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15854769 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/854769
Semiconductor structure with diffusion barrier region and manufacturing method thereof Dec 26, 2017 Issued
Array ( [id] => 12896458 [patent_doc_number] => 20180190661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/854816 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1649 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15854816 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/854816
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Dec 26, 2017 Abandoned
Array ( [id] => 14509579 [patent_doc_number] => 20190198444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => FORMING DUAL METALLIZATION INTERCONNECT STRUCTURES IN SINGLE METALLIZATION LEVEL [patent_app_type] => utility [patent_app_number] => 15/855133 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6060 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855133 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/855133
Forming dual metallization interconnect structures in single metallization level Dec 26, 2017 Issued
Array ( [id] => 16593944 [patent_doc_number] => 10903221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Memory cells and memory arrays [patent_app_type] => utility [patent_app_number] => 15/855089 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6382 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855089 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/855089
Memory cells and memory arrays Dec 26, 2017 Issued
Array ( [id] => 17332451 [patent_doc_number] => 11222919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Spin current magnetization rotational element, spin-orbit torque magnetoresistance effect element, and magnetic memory [patent_app_type] => utility [patent_app_number] => 15/840377 [patent_app_country] => US [patent_app_date] => 2017-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 9647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15840377 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/840377
Spin current magnetization rotational element, spin-orbit torque magnetoresistance effect element, and magnetic memory Dec 12, 2017 Issued
Array ( [id] => 14446777 [patent_doc_number] => 20190181262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => LATERAL INSULATED-GATE BIPOLAR TRANSISTOR AND METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 15/840426 [patent_app_country] => US [patent_app_date] => 2017-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15840426 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/840426
Lateral insulated-gate bipolar transistor and method therefor Dec 12, 2017 Issued
Array ( [id] => 14446733 [patent_doc_number] => 20190181240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => METHODS FOR TRANSISTOR EPITAXIAL STACK FABRICATION [patent_app_type] => utility [patent_app_number] => 15/840392 [patent_app_country] => US [patent_app_date] => 2017-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15840392 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/840392
METHODS FOR TRANSISTOR EPITAXIAL STACK FABRICATION Dec 12, 2017 Abandoned
Array ( [id] => 14446559 [patent_doc_number] => 20190181153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => DIGITAL BLOCKS WITH ELECTRICALLY INSULATED AND ORTHOGONAL POLYSILICON LAYERS [patent_app_type] => utility [patent_app_number] => 15/840335 [patent_app_country] => US [patent_app_date] => 2017-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5189 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15840335 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/840335
Digital blocks with electrically insulated and orthogonal polysilicon layers Dec 12, 2017 Issued
Array ( [id] => 14446733 [patent_doc_number] => 20190181240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => METHODS FOR TRANSISTOR EPITAXIAL STACK FABRICATION [patent_app_type] => utility [patent_app_number] => 15/840392 [patent_app_country] => US [patent_app_date] => 2017-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15840392 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/840392
METHODS FOR TRANSISTOR EPITAXIAL STACK FABRICATION Dec 12, 2017 Abandoned
Array ( [id] => 12631629 [patent_doc_number] => 20180102373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING FERROELECTRIC CAPACITOR AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/836298 [patent_app_country] => US [patent_app_date] => 2017-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18266 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15836298 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/836298
SEMICONDUCTOR DEVICE INCLUDING FERROELECTRIC CAPACITOR AND METHOD OF MANUFACTURING THE SAME Dec 7, 2017 Abandoned
Array ( [id] => 13950811 [patent_doc_number] => 10211184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Apparatus and methods for multi-die packaging [patent_app_type] => utility [patent_app_number] => 15/802943 [patent_app_country] => US [patent_app_date] => 2017-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 5065 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15802943 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/802943
Apparatus and methods for multi-die packaging Nov 2, 2017 Issued
Array ( [id] => 12692707 [patent_doc_number] => 20180122735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => MODULE ASSEMBLY [patent_app_type] => utility [patent_app_number] => 15/796045 [patent_app_country] => US [patent_app_date] => 2017-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15796045 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/796045
Module assembly Oct 26, 2017 Issued
Array ( [id] => 12896107 [patent_doc_number] => 20180190544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => HYBRID-CHANNEL NANO-SHEET FETS [patent_app_type] => utility [patent_app_number] => 15/795975 [patent_app_country] => US [patent_app_date] => 2017-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15795975 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/795975
Hybrid-channel nano-sheets FETs Oct 26, 2017 Issued
Array ( [id] => 14238519 [patent_doc_number] => 20190131432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => SINGLE-CURVATURE CAVITY FOR SEMICONDUCTOR EPITAXY [patent_app_type] => utility [patent_app_number] => 15/795833 [patent_app_country] => US [patent_app_date] => 2017-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15795833 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/795833
Single-curvature cavity for semiconductor epitaxy Oct 26, 2017 Issued
Array ( [id] => 12693298 [patent_doc_number] => 20180122932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/795941 [patent_app_country] => US [patent_app_date] => 2017-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15795941 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/795941
THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE Oct 26, 2017 Abandoned
Array ( [id] => 14333293 [patent_doc_number] => 10297675 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-21 [patent_title] => Dual-curvature cavity for epitaxial semiconductor growth [patent_app_type] => utility [patent_app_number] => 15/795879 [patent_app_country] => US [patent_app_date] => 2017-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3380 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15795879 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/795879
Dual-curvature cavity for epitaxial semiconductor growth Oct 26, 2017 Issued
Array ( [id] => 12181655 [patent_doc_number] => 20180040592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'INTERCONNECT STRUCTURE WITH IMPROVED CONDUCTIVE PROPERTIES AND ASSOCIATED SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 15/788094 [patent_app_country] => US [patent_app_date] => 2017-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4485 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15788094 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/788094
INTERCONNECT STRUCTURE WITH IMPROVED CONDUCTIVE PROPERTIES AND ASSOCIATED SYSTEMS AND METHODS Oct 18, 2017 Abandoned
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