Search

Phat X. Cao

Examiner (ID: 7067)

Most Active Art Unit
2814
Art Unit(s)
2508, 2817, 2814
Total Applications
1687
Issued Applications
1251
Pending Applications
92
Abandoned Applications
373

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11088022 [patent_doc_number] => 20160284990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'SEMICONDUCTOR DEVICES HAVING INSULATING SUBSTRATES AND METHODS OF FORMATION THEREOF' [patent_app_type] => utility [patent_app_number] => 15/181733 [patent_app_country] => US [patent_app_date] => 2016-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6487 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15181733 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/181733
Semiconductor devices having insulating substrates and methods of formation thereof Jun 13, 2016 Issued
Array ( [id] => 11096565 [patent_doc_number] => 20160293534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'CIRCUIT ASSEMBLIES WITH MULTIPLE INTERPOSER SUBSTRATES, AND METHODS OF FABRICATION' [patent_app_type] => utility [patent_app_number] => 15/181872 [patent_app_country] => US [patent_app_date] => 2016-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6779 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15181872 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/181872
Circuit assemblies with multiple interposer substrates, and methods of fabrication Jun 13, 2016 Issued
Array ( [id] => 11701701 [patent_doc_number] => 09691623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-27 [patent_title] => 'Semiconductor structures having low resistance paths throughout a wafer' [patent_app_type] => utility [patent_app_number] => 15/178893 [patent_app_country] => US [patent_app_date] => 2016-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5110 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15178893 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/178893
Semiconductor structures having low resistance paths throughout a wafer Jun 9, 2016 Issued
Array ( [id] => 12454992 [patent_doc_number] => 09984196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-29 [patent_title] => Method and apparatus for modeling multi-terminal MOS device for LVS and PDK [patent_app_type] => utility [patent_app_number] => 15/161780 [patent_app_country] => US [patent_app_date] => 2016-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2948 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15161780 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/161780
Method and apparatus for modeling multi-terminal MOS device for LVS and PDK May 22, 2016 Issued
Array ( [id] => 11036256 [patent_doc_number] => 20160233212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'METAL-INSULATOR-METAL CAPACITOR STRUCTURE' [patent_app_type] => utility [patent_app_number] => 15/098281 [patent_app_country] => US [patent_app_date] => 2016-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7237 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15098281 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/098281
METAL-INSULATOR-METAL CAPACITOR STRUCTURE Apr 12, 2016 Abandoned
Array ( [id] => 11890942 [patent_doc_number] => 09761507 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-12 [patent_title] => 'Stacked rectifiers in a package' [patent_app_type] => utility [patent_app_number] => 15/092671 [patent_app_country] => US [patent_app_date] => 2016-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4512 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15092671 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/092671
Stacked rectifiers in a package Apr 6, 2016 Issued
Array ( [id] => 11990375 [patent_doc_number] => 20170294530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'ELECTRONIC DEVICE INCLUDING A HEMT WITH A SEGMENTED GATE ELECTRODE AND A PROCESS OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/092858 [patent_app_country] => US [patent_app_date] => 2016-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7295 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15092858 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/092858
Electronic device including a HEMT with a segmented gate electrode Apr 6, 2016 Issued
Array ( [id] => 11132349 [patent_doc_number] => 20160329324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-10 [patent_title] => 'Bidirectional Bipolar Power Devices with Two-Surface Optimization of Striped Emitter/Collector Orientation' [patent_app_type] => utility [patent_app_number] => 15/090611 [patent_app_country] => US [patent_app_date] => 2016-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3756 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15090611 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/090611
Bidirectional Bipolar Power Devices with Two-Surface Optimization of Striped Emitter/Collector Orientation Apr 3, 2016 Abandoned
Array ( [id] => 11460198 [patent_doc_number] => 20170054104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/090403 [patent_app_country] => US [patent_app_date] => 2016-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7449 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15090403 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/090403
DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME Apr 3, 2016 Abandoned
Array ( [id] => 11681464 [patent_doc_number] => 09679999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Bidirectional bipolar transistors with two-surface cellular geometries' [patent_app_type] => utility [patent_app_number] => 15/090582 [patent_app_country] => US [patent_app_date] => 2016-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2716 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15090582 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/090582
Bidirectional bipolar transistors with two-surface cellular geometries Apr 3, 2016 Issued
Array ( [id] => 11353671 [patent_doc_number] => 20160372411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/079074 [patent_app_country] => US [patent_app_date] => 2016-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4317 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15079074 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/079074
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME Mar 23, 2016 Abandoned
Array ( [id] => 11974671 [patent_doc_number] => 20170278825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'Apparatus and Methods for Multi-Die Packaging' [patent_app_type] => utility [patent_app_number] => 15/080162 [patent_app_country] => US [patent_app_date] => 2016-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5100 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15080162 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/080162
Apparatus and Methods for Multi-Die Packaging Mar 23, 2016 Abandoned
Array ( [id] => 13019255 [patent_doc_number] => 10032747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Light emitting diode package structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/073710 [patent_app_country] => US [patent_app_date] => 2016-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 5672 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15073710 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/073710
Light emitting diode package structure and manufacturing method thereof Mar 17, 2016 Issued
Array ( [id] => 12147834 [patent_doc_number] => 09882096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-30 [patent_title] => 'Light emitting diode structure and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 15/073715 [patent_app_country] => US [patent_app_date] => 2016-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5430 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15073715 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/073715
Light emitting diode structure and method for manufacturing the same Mar 17, 2016 Issued
Array ( [id] => 12115132 [patent_doc_number] => 09871128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-16 [patent_title] => 'Bipolar semiconductor device with sub-cathode enhancement regions' [patent_app_type] => utility [patent_app_number] => 15/074009 [patent_app_country] => US [patent_app_date] => 2016-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6011 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15074009 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/074009
Bipolar semiconductor device with sub-cathode enhancement regions Mar 17, 2016 Issued
Array ( [id] => 11087697 [patent_doc_number] => 20160284666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'PACKAGE SUBSTRATE AND PACKAGE STRUCTURE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/073707 [patent_app_country] => US [patent_app_date] => 2016-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3508 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15073707 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/073707
Package substrate and package structure using the same Mar 17, 2016 Issued
Array ( [id] => 11079329 [patent_doc_number] => 20160276293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'LIGHT-EMITTING DEVICE AND BACKLIGHT MODULE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/073705 [patent_app_country] => US [patent_app_date] => 2016-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3446 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15073705 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/073705
Light-emitting device and backlight module using the same Mar 17, 2016 Issued
Array ( [id] => 11967292 [patent_doc_number] => 20170271445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'Bipolar Semiconductor Device Having Localized Enhancement Regions' [patent_app_type] => utility [patent_app_number] => 15/073937 [patent_app_country] => US [patent_app_date] => 2016-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5737 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15073937 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/073937
Bipolar Semiconductor Device Having Localized Enhancement Regions Mar 17, 2016 Abandoned
Array ( [id] => 13909577 [patent_doc_number] => 20190043993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => TECHNIQUES FOR FORMING TRANSISTORS INCLUDING GROUP III-V MATERIAL NANOWIRES USING SACRIFICIAL GROUP IV MATERIAL LAYERS [patent_app_type] => utility [patent_app_number] => 16/076550 [patent_app_country] => US [patent_app_date] => 2016-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12146 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16076550 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/076550
Techniques for forming transistors including group III-V material nanowires using sacrificial group IV material layers Mar 10, 2016 Issued
Array ( [id] => 11071561 [patent_doc_number] => 20160268525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'PHOTO-PATTERNABLE GATE DIELECTRICS FOR OFET' [patent_app_type] => utility [patent_app_number] => 15/066548 [patent_app_country] => US [patent_app_date] => 2016-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10558 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15066548 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/066548
Photo-patternable gate dielectrics for OFET Mar 9, 2016 Issued
Menu