Search

Phat X. Cao

Examiner (ID: 7067)

Most Active Art Unit
2814
Art Unit(s)
2508, 2817, 2814
Total Applications
1687
Issued Applications
1251
Pending Applications
92
Abandoned Applications
373

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10993393 [patent_doc_number] => 20160190339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'SEMICONDUCTOR DEVICES WITH CONDUCTIVE CONTACT STRUCTURES HAVING A LARGER METAL SILICIDE CONTACT AREA' [patent_app_type] => utility [patent_app_number] => 15/065998 [patent_app_country] => US [patent_app_date] => 2016-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 7729 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15065998 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/065998
SEMICONDUCTOR DEVICES WITH CONDUCTIVE CONTACT STRUCTURES HAVING A LARGER METAL SILICIDE CONTACT AREA Mar 9, 2016 Abandoned
Array ( [id] => 10993360 [patent_doc_number] => 20160190306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'FINFET DEVICE WITH A SUBSTANTIALLY SELF-ALIGNED ISOLATION REGION POSITIONED UNDER THE CHANNEL REGION' [patent_app_type] => utility [patent_app_number] => 15/063633 [patent_app_country] => US [patent_app_date] => 2016-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8594 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15063633 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/063633
FINFET DEVICE WITH A SUBSTANTIALLY SELF-ALIGNED ISOLATION REGION POSITIONED UNDER THE CHANNEL REGION Mar 7, 2016 Abandoned
Array ( [id] => 11111042 [patent_doc_number] => 20160308012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/059673 [patent_app_country] => US [patent_app_date] => 2016-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 68 [patent_figures_cnt] => 68 [patent_no_of_words] => 16330 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15059673 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/059673
Finfet semiconductor device and method of manufacturing the same Mar 2, 2016 Issued
Array ( [id] => 11495459 [patent_doc_number] => 20170069644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/059653 [patent_app_country] => US [patent_app_date] => 2016-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7043 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15059653 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/059653
Stacked semiconductor device Mar 2, 2016 Issued
Array ( [id] => 10984546 [patent_doc_number] => 20160181491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'OPTOELECTRONIC SEMICONDUCTOR COMPONENT' [patent_app_type] => utility [patent_app_number] => 15/058667 [patent_app_country] => US [patent_app_date] => 2016-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6851 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15058667 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/058667
Optoelectronic semiconductor component Mar 1, 2016 Issued
Array ( [id] => 12181729 [patent_doc_number] => 20180040665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'DISPLAY APPARATUS AND ILLUMINATION APPARATUS, AND LIGHT EMITTING ELEMENT AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/554914 [patent_app_country] => US [patent_app_date] => 2016-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 27043 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15554914 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/554914
DISPLAY APPARATUS AND ILLUMINATION APPARATUS, AND LIGHT EMITTING ELEMENT AND SEMICONDUCTOR DEVICE Feb 15, 2016 Abandoned
Array ( [id] => 10809506 [patent_doc_number] => 20160155665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => '3D Integrated Circuit and Methods of Forming the Same' [patent_app_type] => utility [patent_app_number] => 15/018422 [patent_app_country] => US [patent_app_date] => 2016-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15018422 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/018422
3D integrated circuit and methods of forming the same Feb 7, 2016 Issued
Array ( [id] => 11539746 [patent_doc_number] => 09614168 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-04 [patent_title] => 'Flexible display panel with bent substrate' [patent_app_type] => utility [patent_app_number] => 14/987129 [patent_app_country] => US [patent_app_date] => 2016-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 4315 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14987129 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/987129
Flexible display panel with bent substrate Jan 3, 2016 Issued
Array ( [id] => 10765396 [patent_doc_number] => 20160111552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'Semiconductor Device And Manufacturing Method Thereof' [patent_app_type] => utility [patent_app_number] => 14/974627 [patent_app_country] => US [patent_app_date] => 2015-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13861 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14974627 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/974627
Semiconductor device and manufacturing method thereof Dec 17, 2015 Issued
Array ( [id] => 10765335 [patent_doc_number] => 20160111492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'Semiconductor Film with Adhesion Layer and Method for Forming the Same' [patent_app_type] => utility [patent_app_number] => 14/971484 [patent_app_country] => US [patent_app_date] => 2015-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4337 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14971484 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/971484
Semiconductor film with adhesion layer and method for forming the same Dec 15, 2015 Issued
Array ( [id] => 10753153 [patent_doc_number] => 20160099305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'Integrated Circuitry and Methods of Forming Transistors' [patent_app_type] => utility [patent_app_number] => 14/966927 [patent_app_country] => US [patent_app_date] => 2015-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5360 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14966927 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/966927
Integrated circuitry and methods of forming transistors Dec 10, 2015 Issued
Array ( [id] => 10740749 [patent_doc_number] => 20160086901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'Bump-on-Trace Structures with High Assembly Yield' [patent_app_type] => utility [patent_app_number] => 14/954175 [patent_app_country] => US [patent_app_date] => 2015-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3564 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14954175 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/954175
Bump-on-trace structures with high assembly yield Nov 29, 2015 Issued
Array ( [id] => 10697017 [patent_doc_number] => 20160043164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'Capacitor and Method of Forming a Capacitor' [patent_app_type] => utility [patent_app_number] => 14/918190 [patent_app_country] => US [patent_app_date] => 2015-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4690 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14918190 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/918190
Capacitor and method of forming a capacitor Oct 19, 2015 Issued
Array ( [id] => 10689582 [patent_doc_number] => 20160035728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'RETROGRADE DOPED LAYER FOR DEVICE ISOLATION' [patent_app_type] => utility [patent_app_number] => 14/882308 [patent_app_country] => US [patent_app_date] => 2015-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4417 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14882308 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/882308
RETROGRADE DOPED LAYER FOR DEVICE ISOLATION Oct 12, 2015 Abandoned
Array ( [id] => 12969268 [patent_doc_number] => 09875996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-23 [patent_title] => Composite substrate for light emitting device and LED module with the same [patent_app_type] => utility [patent_app_number] => 14/881126 [patent_app_country] => US [patent_app_date] => 2015-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3803 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14881126 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/881126
Composite substrate for light emitting device and LED module with the same Oct 11, 2015 Issued
Array ( [id] => 10681543 [patent_doc_number] => 20160027688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-28 [patent_title] => 'Method Of Preventing Pattern Collapse' [patent_app_type] => utility [patent_app_number] => 14/873301 [patent_app_country] => US [patent_app_date] => 2015-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5290 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14873301 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/873301
Method of preventing pattern collapse Oct 1, 2015 Issued
Array ( [id] => 10479351 [patent_doc_number] => 20150364368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'SEMICONDUCTOR STRUCTURES HAVING LOW RESISTANCE PATHS THROUGHOUT A WAFER' [patent_app_type] => utility [patent_app_number] => 14/832021 [patent_app_country] => US [patent_app_date] => 2015-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5113 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14832021 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/832021
Semiconductor structures having low resistance paths throughout a wafer Aug 20, 2015 Issued
Array ( [id] => 14955049 [patent_doc_number] => 10438803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Semiconductor structures having low resistance paths throughout a wafer [patent_app_type] => utility [patent_app_number] => 14/832024 [patent_app_country] => US [patent_app_date] => 2015-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4996 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14832024 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/832024
Semiconductor structures having low resistance paths throughout a wafer Aug 20, 2015 Issued
Array ( [id] => 10479399 [patent_doc_number] => 20150364416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'SEMICONDUCTOR STRUCTURES HAVING LOW RESISTANCE PATHS THROUGHOUT A WAFER' [patent_app_type] => utility [patent_app_number] => 14/832019 [patent_app_country] => US [patent_app_date] => 2015-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5108 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14832019 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/832019
Semiconductor structures having low resistance paths throughout a wafer Aug 20, 2015 Issued
Array ( [id] => 12089088 [patent_doc_number] => 09842822 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-12 [patent_title] => 'Semiconductor packages with socket plug interconnection structures' [patent_app_type] => utility [patent_app_number] => 14/831463 [patent_app_country] => US [patent_app_date] => 2015-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 5476 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14831463 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/831463
Semiconductor packages with socket plug interconnection structures Aug 19, 2015 Issued
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