Search

Phat X. Cao

Examiner (ID: 4407, Phone: (571)272-1703 , Office: P/2817 )

Most Active Art Unit
2814
Art Unit(s)
2814, 2817, 2508
Total Applications
1671
Issued Applications
1258
Pending Applications
66
Abandoned Applications
373

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4627429 [patent_doc_number] => RE042653 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2011-08-30 [patent_title] => 'Semiconductor package with heat dissipating structure' [patent_app_type] => reissue [patent_app_number] => 12/722009 [patent_app_country] => US [patent_app_date] => 2010-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2974 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/042/RE042653.pdf [firstpage_image] =>[orig_patent_app_number] => 12722009 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/722009
Semiconductor package with heat dissipating structure Mar 10, 2010 Issued
Array ( [id] => 6392567 [patent_doc_number] => 20100163921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'SEMICONDUCTOR CHIP ASSEMBLY WITH ALUMINUM POST/BASE HEAT SPREADER AND SILVER/COPPER CONDUCTIVE TRACE' [patent_app_type] => utility [patent_app_number] => 12/721551 [patent_app_country] => US [patent_app_date] => 2010-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 18141 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20100163921.pdf [firstpage_image] =>[orig_patent_app_number] => 12721551 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/721551
Semiconductor chip assembly with aluminum post/base heat spreader and silver/copper conductive trace Mar 9, 2010 Issued
Array ( [id] => 8457908 [patent_doc_number] => 08293574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Semiconductor device having a plurality of semiconductor constructs' [patent_app_type] => utility [patent_app_number] => 12/719411 [patent_app_country] => US [patent_app_date] => 2010-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6503 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12719411 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/719411
Semiconductor device having a plurality of semiconductor constructs Mar 7, 2010 Issued
Array ( [id] => 6286168 [patent_doc_number] => 20100157669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'Floating Gate Inverter Type Memory Cell And Array' [patent_app_type] => utility [patent_app_number] => 12/715762 [patent_app_country] => US [patent_app_date] => 2010-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10100 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20100157669.pdf [firstpage_image] =>[orig_patent_app_number] => 12715762 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/715762
Floating gate inverter type memory cell and array Mar 1, 2010 Issued
Array ( [id] => 4511102 [patent_doc_number] => 07915745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-29 [patent_title] => 'Multi-port memory device having serial input/output interface' [patent_app_type] => utility [patent_app_number] => 12/698519 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1833 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/915/07915745.pdf [firstpage_image] =>[orig_patent_app_number] => 12698519 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/698519
Multi-port memory device having serial input/output interface Feb 1, 2010 Issued
Array ( [id] => 6342410 [patent_doc_number] => 20100084703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE INCLUDING A STACKED GATE HAVING A CHARGE STORAGE LAYER AND A CONTROL GATE, AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/634406 [patent_app_country] => US [patent_app_date] => 2009-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11409 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20100084703.pdf [firstpage_image] =>[orig_patent_app_number] => 12634406 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/634406
Semiconductor memory device including a stacked gate having a charge storage layer and a control gate, and method of manufacturing the same Dec 8, 2009 Issued
Array ( [id] => 8270799 [patent_doc_number] => 08212305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'Semiconductor device with improved insulating film and floating gate arrangement to decrease memory cell size without reduction of capacitance' [patent_app_type] => utility [patent_app_number] => 12/633815 [patent_app_country] => US [patent_app_date] => 2009-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 94 [patent_no_of_words] => 20451 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12633815 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/633815
Semiconductor device with improved insulating film and floating gate arrangement to decrease memory cell size without reduction of capacitance Dec 8, 2009 Issued
Array ( [id] => 54863 [patent_doc_number] => 07768012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'LCD pixel array structure' [patent_app_type] => utility [patent_app_number] => 12/628316 [patent_app_country] => US [patent_app_date] => 2009-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1885 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/768/07768012.pdf [firstpage_image] =>[orig_patent_app_number] => 12628316 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/628316
LCD pixel array structure Nov 30, 2009 Issued
Array ( [id] => 6304217 [patent_doc_number] => 20100109050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'FIELD EFFECT TRANSISTOR WITH INDEPENDENTLY BIASED GATES' [patent_app_type] => utility [patent_app_number] => 12/612420 [patent_app_country] => US [patent_app_date] => 2009-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3275 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20100109050.pdf [firstpage_image] =>[orig_patent_app_number] => 12612420 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/612420
FIELD EFFECT TRANSISTOR WITH INDEPENDENTLY BIASED GATES Nov 3, 2009 Abandoned
Array ( [id] => 6098776 [patent_doc_number] => 20110163345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-07 [patent_title] => 'LEAD, WIRING MEMBER, PACKAGE COMPONENT, METAL COMPONENT WITH RESIN, RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE, AND METHODS FOR PRODUCING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/063446 [patent_app_country] => US [patent_app_date] => 2009-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 23518 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20110163345.pdf [firstpage_image] =>[orig_patent_app_number] => 13063446 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/063446
Lead, wiring member, package component, metal component with resin, resin-encapsulated semiconductor device, and methods for producing the same Oct 27, 2009 Issued
Array ( [id] => 8662001 [patent_doc_number] => RE044019 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2013-02-19 [patent_title] => 'Stacked semiconductor module' [patent_app_type] => reissue [patent_app_number] => 12/605303 [patent_app_country] => US [patent_app_date] => 2009-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3160 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12605303 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/605303
Stacked semiconductor module Oct 22, 2009 Issued
Array ( [id] => 8543258 [patent_doc_number] => 08318547 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-11-27 [patent_title] => 'Integrated circuit package with electrically isolated leads' [patent_app_type] => utility [patent_app_number] => 12/568599 [patent_app_country] => US [patent_app_date] => 2009-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3665 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12568599 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/568599
Integrated circuit package with electrically isolated leads Sep 27, 2009 Issued
Array ( [id] => 8340107 [patent_doc_number] => 08242030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Activation of graphene buffer layers on silicon carbide by ultra low temperature oxidation' [patent_app_type] => utility [patent_app_number] => 12/566870 [patent_app_country] => US [patent_app_date] => 2009-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3179 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12566870 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/566870
Activation of graphene buffer layers on silicon carbide by ultra low temperature oxidation Sep 24, 2009 Issued
Array ( [id] => 4431850 [patent_doc_number] => 07968395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Systems and methods for reducing contact to gate shorts' [patent_app_type] => utility [patent_app_number] => 12/567075 [patent_app_country] => US [patent_app_date] => 2009-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 3494 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/968/07968395.pdf [firstpage_image] =>[orig_patent_app_number] => 12567075 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/567075
Systems and methods for reducing contact to gate shorts Sep 24, 2009 Issued
Array ( [id] => 6463595 [patent_doc_number] => 20100006927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'Charge Balance Techniques for Power Devices' [patent_app_type] => utility [patent_app_number] => 12/562025 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3282 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20100006927.pdf [firstpage_image] =>[orig_patent_app_number] => 12562025 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/562025
Charge balance techniques for power devices Sep 16, 2009 Issued
Array ( [id] => 7550580 [patent_doc_number] => 08062912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Method of making a semiconductor chip assembly with a post/base heat spreader and horizontal signal routing' [patent_app_type] => utility [patent_app_number] => 12/558526 [patent_app_country] => US [patent_app_date] => 2009-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 45 [patent_no_of_words] => 17697 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/062/08062912.pdf [firstpage_image] =>[orig_patent_app_number] => 12558526 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/558526
Method of making a semiconductor chip assembly with a post/base heat spreader and horizontal signal routing Sep 12, 2009 Issued
Array ( [id] => 4624120 [patent_doc_number] => 08003415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Method of making a semiconductor chip assembly with a post/base heat spreader and vertical signal routing' [patent_app_type] => utility [patent_app_number] => 12/558527 [patent_app_country] => US [patent_app_date] => 2009-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 38 [patent_no_of_words] => 17245 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/003/08003415.pdf [firstpage_image] =>[orig_patent_app_number] => 12558527 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/558527
Method of making a semiconductor chip assembly with a post/base heat spreader and vertical signal routing Sep 12, 2009 Issued
Array ( [id] => 6021351 [patent_doc_number] => 20110049677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'Buried Layer of An Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 12/549869 [patent_app_country] => US [patent_app_date] => 2009-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3996 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20110049677.pdf [firstpage_image] =>[orig_patent_app_number] => 12549869 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/549869
Buried layer of an integrated circuit Aug 27, 2009 Issued
Array ( [id] => 6562768 [patent_doc_number] => 20100059842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'IMAGE SENSOR AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/549619 [patent_app_country] => US [patent_app_date] => 2009-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3220 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20100059842.pdf [firstpage_image] =>[orig_patent_app_number] => 12549619 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/549619
IMAGE SENSOR AND MANUFACTURING METHOD THEREOF Aug 27, 2009 Abandoned
Array ( [id] => 5364790 [patent_doc_number] => 20090302349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'STRAINED GERMANIUM FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/540216 [patent_app_country] => US [patent_app_date] => 2009-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2490 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20090302349.pdf [firstpage_image] =>[orig_patent_app_number] => 12540216 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/540216
STRAINED GERMANIUM FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME Aug 11, 2009 Abandoned
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