
Phat X. Cao
Examiner (ID: 249, Phone: (571)272-1703 , Office: P/2817 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2508, 2814, 2817 |
| Total Applications | 1655 |
| Issued Applications | 1258 |
| Pending Applications | 44 |
| Abandoned Applications | 373 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18205607
[patent_doc_number] => 11588014
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-21
[patent_title] => Epitaxial structure
[patent_app_type] => utility
[patent_app_number] => 17/689993
[patent_app_country] => US
[patent_app_date] => 2022-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 4662
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17689993
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/689993 | Epitaxial structure | Mar 8, 2022 | Issued |
Array
(
[id] => 17692469
[patent_doc_number] => 20220199762
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-23
[patent_title] => EPITAXIAL STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/689995
[patent_app_country] => US
[patent_app_date] => 2022-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4682
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17689995
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/689995 | Epitaxial structure | Mar 8, 2022 | Issued |
Array
(
[id] => 17676945
[patent_doc_number] => 20220190112
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-16
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/686700
[patent_app_country] => US
[patent_app_date] => 2022-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9373
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17686700
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/686700 | Semiconductor device having increased contact area between a source/drain pattern and an active contact | Mar 3, 2022 | Issued |
Array
(
[id] => 18024693
[patent_doc_number] => 20220376192
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-24
[patent_title] => DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/668505
[patent_app_country] => US
[patent_app_date] => 2022-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7226
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17668505
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/668505 | Display device and method of manufacturing the same | Feb 9, 2022 | Issued |
Array
(
[id] => 17615386
[patent_doc_number] => 20220157666
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-19
[patent_title] => HYBRID-CHANNEL NANO-SHEET FETS
[patent_app_type] => utility
[patent_app_number] => 17/592470
[patent_app_country] => US
[patent_app_date] => 2022-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5353
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 282
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17592470
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/592470 | Hybrid-channel nano-sheet FETs | Feb 2, 2022 | Issued |
Array
(
[id] => 20443080
[patent_doc_number] => 12513926
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-30
[patent_title] => Semiconductor device and semiconductor module
[patent_app_type] => utility
[patent_app_number] => 17/649817
[patent_app_country] => US
[patent_app_date] => 2022-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 34
[patent_no_of_words] => 4062
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 450
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17649817
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/649817 | Semiconductor device and semiconductor module | Feb 2, 2022 | Issued |
Array
(
[id] => 19705166
[patent_doc_number] => 12199214
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-14
[patent_title] => Light emitting diode with high efficiency
[patent_app_type] => utility
[patent_app_number] => 17/586804
[patent_app_country] => US
[patent_app_date] => 2022-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 23
[patent_no_of_words] => 20628
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 275
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17586804
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/586804 | Light emitting diode with high efficiency | Jan 27, 2022 | Issued |
Array
(
[id] => 20080920
[patent_doc_number] => 12354998
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-08
[patent_title] => Packaged electronic system formed by electrically connected and galvanically isolated dice
[patent_app_type] => utility
[patent_app_number] => 17/580480
[patent_app_country] => US
[patent_app_date] => 2022-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 13
[patent_no_of_words] => 1072
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 418
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580480
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/580480 | Packaged electronic system formed by electrically connected and galvanically isolated dice | Jan 19, 2022 | Issued |
Array
(
[id] => 20334474
[patent_doc_number] => 12464770
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-04
[patent_title] => Semiconductor devices having vertical channel transistor structures and methods of fabricating the same
[patent_app_type] => utility
[patent_app_number] => 17/578893
[patent_app_country] => US
[patent_app_date] => 2022-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 28
[patent_no_of_words] => 4526
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578893
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/578893 | Semiconductor devices having vertical channel transistor structures and methods of fabricating the same | Jan 18, 2022 | Issued |
Array
(
[id] => 17963843
[patent_doc_number] => 20220344424
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-27
[patent_title] => DISPLAY DEVICE AND METHOD OF MANUFACTURING DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/568242
[patent_app_country] => US
[patent_app_date] => 2022-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18333
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568242
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/568242 | Display device and method of manufacturing display device | Jan 3, 2022 | Issued |
Array
(
[id] => 18179302
[patent_doc_number] => 20230040031
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-09
[patent_title] => METHOD OF FORMING METAL GRID, BACKSIDE-ILLUMINATED IMAGE SENSOR AND METHOD OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/566386
[patent_app_country] => US
[patent_app_date] => 2021-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7472
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17566386
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/566386 | Method of forming metal grid, backside-illuminated image sensor and method of forming the same | Dec 29, 2021 | Issued |
Array
(
[id] => 19900240
[patent_doc_number] => 12278177
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-15
[patent_title] => Semiconductor device manufacturing method
[patent_app_type] => utility
[patent_app_number] => 17/521959
[patent_app_country] => US
[patent_app_date] => 2021-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 1094
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17521959
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/521959 | Semiconductor device manufacturing method | Nov 8, 2021 | Issued |
Array
(
[id] => 17630679
[patent_doc_number] => 20220165694
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-26
[patent_title] => SEMICONDUCTOR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/510348
[patent_app_country] => US
[patent_app_date] => 2021-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3194
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -26
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510348
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/510348 | SEMICONDUCTOR STRUCTURE | Oct 24, 2021 | Abandoned |
Array
(
[id] => 18271944
[patent_doc_number] => 20230093186
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-23
[patent_title] => SEMICONDUCTOR DEVICE HAVING SOLDER-FREE DIE CONNECTION TO REDISTRIBUTION LAYER
[patent_app_type] => utility
[patent_app_number] => 17/479871
[patent_app_country] => US
[patent_app_date] => 2021-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7773
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17479871
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/479871 | SEMICONDUCTOR DEVICE HAVING SOLDER-FREE DIE CONNECTION TO REDISTRIBUTION LAYER | Sep 19, 2021 | Pending |
Array
(
[id] => 20317447
[patent_doc_number] => 12455999
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-28
[patent_title] => Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level
[patent_app_type] => utility
[patent_app_number] => 17/473039
[patent_app_country] => US
[patent_app_date] => 2021-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 0
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473039
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/473039 | Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level | Sep 12, 2021 | Issued |
Array
(
[id] => 18241512
[patent_doc_number] => 20230073823
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-09
[patent_title] => PACKAGE COMPRISING A SUBSTRATE WITH HIGH-DENSITY INTERCONNECTS
[patent_app_type] => utility
[patent_app_number] => 17/471061
[patent_app_country] => US
[patent_app_date] => 2021-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10539
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17471061
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/471061 | PACKAGE COMPRISING A SUBSTRATE WITH HIGH-DENSITY INTERCONNECTS | Sep 8, 2021 | Abandoned |
Array
(
[id] => 19733742
[patent_doc_number] => 12211743
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-28
[patent_title] => Method of forming a metal liner for interconnect structures
[patent_app_type] => utility
[patent_app_number] => 17/466732
[patent_app_country] => US
[patent_app_date] => 2021-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 9291
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17466732
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/466732 | Method of forming a metal liner for interconnect structures | Sep 2, 2021 | Issued |
Array
(
[id] => 17847923
[patent_doc_number] => 11437308
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-06
[patent_title] => Packaging glass substrate for semiconductor, a packaging substrate for semiconductor, and a semiconductor apparatus
[patent_app_type] => utility
[patent_app_number] => 17/462254
[patent_app_country] => US
[patent_app_date] => 2021-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 11741
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462254
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/462254 | Packaging glass substrate for semiconductor, a packaging substrate for semiconductor, and a semiconductor apparatus | Aug 30, 2021 | Issued |
Array
(
[id] => 19828763
[patent_doc_number] => 12249555
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-11
[patent_title] => Semiconductor device package including a thermal conductive layer and methods of forming the same
[patent_app_type] => utility
[patent_app_number] => 17/380360
[patent_app_country] => US
[patent_app_date] => 2021-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 7256
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17380360
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/380360 | Semiconductor device package including a thermal conductive layer and methods of forming the same | Jul 19, 2021 | Issued |
Array
(
[id] => 17963790
[patent_doc_number] => 20220344371
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-27
[patent_title] => ARRAYED SWITCH CIRCUIT, SWITCHING ELEMENT AND SYSTEM CHIP PACKAGE STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/372132
[patent_app_country] => US
[patent_app_date] => 2021-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6072
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372132
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/372132 | Arrayed switch circuit, switching element and system chip package structure | Jul 8, 2021 | Issued |