Search

Phat X. Cao

Examiner (ID: 710, Phone: (571)272-1703 , Office: P/2817 )

Most Active Art Unit
2814
Art Unit(s)
2814, 2817, 2508
Total Applications
1656
Issued Applications
1258
Pending Applications
45
Abandoned Applications
373

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17963790 [patent_doc_number] => 20220344371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => ARRAYED SWITCH CIRCUIT, SWITCHING ELEMENT AND SYSTEM CHIP PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/372132 [patent_app_country] => US [patent_app_date] => 2021-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372132 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/372132
Arrayed switch circuit, switching element and system chip package structure Jul 8, 2021 Issued
Array ( [id] => 18061774 [patent_doc_number] => 20220392861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => ELECTRONIC PACKAGE AND CARRIER THEREOF AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/369029 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369029 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/369029
Electronic package and carrier thereof and method for manufacturing the same Jul 6, 2021 Issued
Array ( [id] => 17347124 [patent_doc_number] => 20220013455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => WIRING SUBSTRATE AND METHOD FOR MANUFACTURING WIRING SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/361460 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5746 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17361460 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/361460
WIRING SUBSTRATE AND METHOD FOR MANUFACTURING WIRING SUBSTRATE Jun 28, 2021 Pending
Array ( [id] => 18097535 [patent_doc_number] => 20220415876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => CONTROLLED ELECTROSTATIC DISCHARGING TO AVOID LOADING ON INPUT/OUTPUT PINS [patent_app_type] => utility [patent_app_number] => 17/360832 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4455 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17360832 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/360832
CONTROLLED ELECTROSTATIC DISCHARGING TO AVOID LOADING ON INPUT/OUTPUT PINS Jun 27, 2021 Abandoned
Array ( [id] => 18068176 [patent_doc_number] => 20220399264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => INTERCONNECTION STRUCTURE FOR INTEGRATED CIRCUIT PACKAGE AND THE METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/343942 [patent_app_country] => US [patent_app_date] => 2021-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3138 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17343942 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/343942
INTERCONNECTION STRUCTURE FOR INTEGRATED CIRCUIT PACKAGE AND THE METHOD THEREOF Jun 9, 2021 Abandoned
Array ( [id] => 17752773 [patent_doc_number] => 20220230978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => HYBRID MICRO-BUMP INTEGRATION WITH REDISTRIBUTION LAYER [patent_app_type] => utility [patent_app_number] => 17/326941 [patent_app_country] => US [patent_app_date] => 2021-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10009 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17326941 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/326941
Hybrid micro-bump integration with redistribution layer May 20, 2021 Issued
Array ( [id] => 17318918 [patent_doc_number] => 20210407968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => DEVICE INCLUDING FIRST STRUCTURE HAVING PERIPHERAL CIRCUIT AND SECOND STRUCTURE HAVING GATE LAYERS [patent_app_type] => utility [patent_app_number] => 17/315716 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12232 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315716 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/315716
Device including first structure having peripheral circuit and second structure having gate layers May 9, 2021 Issued
Array ( [id] => 17010876 [patent_doc_number] => 20210242037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR INTERCONNECT STRUCTURE AND SEMICONDUCTOR STRUCTURE THEREOF [patent_app_type] => utility [patent_app_number] => 17/236933 [patent_app_country] => US [patent_app_date] => 2021-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4536 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17236933 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/236933
Method for fabricating semiconductor interconnect structure and semiconductor structure thereof Apr 20, 2021 Issued
Array ( [id] => 17188820 [patent_doc_number] => 20210335705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => TERMINAL STRUCTURE AND WIRING SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/235690 [patent_app_country] => US [patent_app_date] => 2021-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17235690 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/235690
Terminal structure and wiring substrate Apr 19, 2021 Issued
Array ( [id] => 19733777 [patent_doc_number] => 12211779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Semiconductor package having multiple substrates [patent_app_type] => utility [patent_app_number] => 17/233081 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 9076 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17233081 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/233081
Semiconductor package having multiple substrates Apr 15, 2021 Issued
Array ( [id] => 19705119 [patent_doc_number] => 12199167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Gate line plug structures for advanced integrated circuit structure fabrication [patent_app_type] => utility [patent_app_number] => 17/216550 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 121 [patent_figures_cnt] => 224 [patent_no_of_words] => 73914 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17216550 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/216550
Gate line plug structures for advanced integrated circuit structure fabrication Mar 28, 2021 Issued
Array ( [id] => 18670112 [patent_doc_number] => 11777024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Nitride semiconductor device and fabrication method therefor [patent_app_type] => utility [patent_app_number] => 17/212619 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 39 [patent_no_of_words] => 21492 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17212619 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/212619
Nitride semiconductor device and fabrication method therefor Mar 24, 2021 Issued
Array ( [id] => 17926029 [patent_doc_number] => 11469293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 17/209076 [patent_app_country] => US [patent_app_date] => 2021-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 8942 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17209076 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/209076
Display device Mar 21, 2021 Issued
Array ( [id] => 20148399 [patent_doc_number] => 12382760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Light emitting diode package [patent_app_type] => utility [patent_app_number] => 17/193447 [patent_app_country] => US [patent_app_date] => 2021-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 3389 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17193447 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/193447
Light emitting diode package Mar 4, 2021 Issued
Array ( [id] => 17893401 [patent_doc_number] => 11456385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-27 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/172261 [patent_app_country] => US [patent_app_date] => 2021-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 30 [patent_no_of_words] => 13279 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17172261 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/172261
Semiconductor device and manufacturing method thereof Feb 9, 2021 Issued
Array ( [id] => 17797630 [patent_doc_number] => 20220256722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/169226 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6041 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17169226 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/169226
ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME Feb 4, 2021 Abandoned
Array ( [id] => 16850899 [patent_doc_number] => 20210151644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => LIGHT EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 17/161508 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17161508 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/161508
Light emitting device Jan 27, 2021 Issued
Array ( [id] => 17752710 [patent_doc_number] => 20220230915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/151067 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6000 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17151067 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/151067
Electronic device package and method of manufacturing the same Jan 14, 2021 Issued
Array ( [id] => 17347123 [patent_doc_number] => 20220013454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/149216 [patent_app_country] => US [patent_app_date] => 2021-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17149216 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/149216
Semiconductor package Jan 13, 2021 Issued
Array ( [id] => 16850608 [patent_doc_number] => 20210151353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => 3D Integrated Circuit and Methods of Forming the Same [patent_app_type] => utility [patent_app_number] => 17/140794 [patent_app_country] => US [patent_app_date] => 2021-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4154 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17140794 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/140794
3D Integrated Circuit and Methods of Forming the Same Jan 3, 2021 Pending
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