Search

Phat X. Cao

Examiner (ID: 7067)

Most Active Art Unit
2814
Art Unit(s)
2508, 2817, 2814
Total Applications
1687
Issued Applications
1251
Pending Applications
92
Abandoned Applications
373

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16904842 [patent_doc_number] => 20210183758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => CONDUCTIVE POLYGON POWER AND GROUND INTERCONNECTS FOR INTEGRATED-CIRCUIT PACKAGES [patent_app_type] => utility [patent_app_number] => 17/030080 [patent_app_country] => US [patent_app_date] => 2020-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17030080 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/030080
CONDUCTIVE POLYGON POWER AND GROUND INTERCONNECTS FOR INTEGRATED-CIRCUIT PACKAGES Sep 22, 2020 Abandoned
Array ( [id] => 17486004 [patent_doc_number] => 20220093508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => VIA STRUCTURES OF PASSIVE SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/027661 [patent_app_country] => US [patent_app_date] => 2020-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17027661 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/027661
Via structures of passive semiconductor devices Sep 20, 2020 Issued
Array ( [id] => 19229671 [patent_doc_number] => 12009315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Component carrier structure connectable by electrically conductive connection medium in recess with cavity having surface profile [patent_app_type] => utility [patent_app_number] => 16/948106 [patent_app_country] => US [patent_app_date] => 2020-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 9120 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 348 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16948106 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/948106
Component carrier structure connectable by electrically conductive connection medium in recess with cavity having surface profile Sep 2, 2020 Issued
Array ( [id] => 18911460 [patent_doc_number] => 11874437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Black structure and self-luminous image display device comprising same [patent_app_type] => utility [patent_app_number] => 17/007396 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 10618 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007396 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/007396
Black structure and self-luminous image display device comprising same Aug 30, 2020 Issued
Array ( [id] => 16516227 [patent_doc_number] => 20200395485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => PROCESS TO REDUCE PLASMA INDUCED DAMAGE [patent_app_type] => utility [patent_app_number] => 17/006261 [patent_app_country] => US [patent_app_date] => 2020-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17006261 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/006261
Process to reduce plasma induced damage Aug 27, 2020 Issued
Array ( [id] => 16677358 [patent_doc_number] => 20210066124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/006000 [patent_app_country] => US [patent_app_date] => 2020-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17006000 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/006000
SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF Aug 27, 2020 Abandoned
Array ( [id] => 18951011 [patent_doc_number] => 11894317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Package structure and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/003883 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 11974 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003883 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/003883
Package structure and method for manufacturing the same Aug 25, 2020 Issued
Array ( [id] => 17448198 [patent_doc_number] => 20220068703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => METAL INTERCONNECT WRAP AROUND WITH GRAPHENE [patent_app_type] => utility [patent_app_number] => 17/002127 [patent_app_country] => US [patent_app_date] => 2020-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8263 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17002127 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/002127
METAL INTERCONNECT WRAP AROUND WITH GRAPHENE Aug 24, 2020 Abandoned
Array ( [id] => 18759819 [patent_doc_number] => 11810857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Via for semiconductor device and method [patent_app_type] => utility [patent_app_number] => 17/001917 [patent_app_country] => US [patent_app_date] => 2020-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 9295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17001917 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/001917
Via for semiconductor device and method Aug 24, 2020 Issued
Array ( [id] => 17431851 [patent_doc_number] => 20220059560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => METHODS OF FORMING MICROELECTRONIC DEVICES AND MEMORY DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/000809 [patent_app_country] => US [patent_app_date] => 2020-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12134 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17000809 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/000809
Methods of forming microelectronic devices and memory devices Aug 23, 2020 Issued
Array ( [id] => 17870854 [patent_doc_number] => 20220293591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => ELECTRONIC CIRCUITS AND CIRCUIT ELEMENTS [patent_app_type] => utility [patent_app_number] => 17/636090 [patent_app_country] => US [patent_app_date] => 2020-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24071 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -43 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17636090 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/636090
ELECTRONIC CIRCUITS AND CIRCUIT ELEMENTS Aug 18, 2020 Pending
Array ( [id] => 17607139 [patent_doc_number] => 11335631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Power delivery device and method [patent_app_type] => utility [patent_app_number] => 16/994653 [patent_app_country] => US [patent_app_date] => 2020-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5936 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16994653 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/994653
Power delivery device and method Aug 15, 2020 Issued
Array ( [id] => 18639556 [patent_doc_number] => 11764179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Semiconductor device package [patent_app_type] => utility [patent_app_number] => 16/994483 [patent_app_country] => US [patent_app_date] => 2020-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 32 [patent_no_of_words] => 8314 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16994483 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/994483
Semiconductor device package Aug 13, 2020 Issued
Array ( [id] => 17402875 [patent_doc_number] => 20220044966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => METHODS FOR SUB-LITHOGRAPHY RESOLUTION PATTERNING [patent_app_type] => utility [patent_app_number] => 16/989019 [patent_app_country] => US [patent_app_date] => 2020-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16989019 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/989019
Methods for sub-lithography resolution patterning Aug 9, 2020 Issued
Array ( [id] => 18304453 [patent_doc_number] => 11626367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 16/988831 [patent_app_country] => US [patent_app_date] => 2020-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 31 [patent_no_of_words] => 8195 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 431 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16988831 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/988831
Semiconductor package Aug 9, 2020 Issued
Array ( [id] => 17040651 [patent_doc_number] => 20210257287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => CHIP PACKAGE AND CIRCUIT BOARD THEREOF [patent_app_type] => utility [patent_app_number] => 16/986415 [patent_app_country] => US [patent_app_date] => 2020-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2087 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16986415 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/986415
CHIP PACKAGE AND CIRCUIT BOARD THEREOF Aug 5, 2020 Abandoned
Array ( [id] => 17055873 [patent_doc_number] => 20210265307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => SEMICONDUCTOR PACKAGES INCLUDING STACK MODULES COMPRISED OF INTERPOSING BRIDGES AND SEMICONDUCTOR DIES [patent_app_type] => utility [patent_app_number] => 16/984854 [patent_app_country] => US [patent_app_date] => 2020-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12387 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16984854 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/984854
Semiconductor packages including stack modules comprised of interposing bridges and semiconductor dies Aug 3, 2020 Issued
Array ( [id] => 16995441 [patent_doc_number] => 20210233861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => Liner-Free Conductive Structures with Anchor Points [patent_app_type] => utility [patent_app_number] => 16/936335 [patent_app_country] => US [patent_app_date] => 2020-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8284 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16936335 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/936335
Liner-free conductive structures with anchor points Jul 21, 2020 Issued
Array ( [id] => 16873540 [patent_doc_number] => 20210167007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => REDISTRIBUTION STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/931129 [patent_app_country] => US [patent_app_date] => 2020-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8480 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16931129 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/931129
REDISTRIBUTION STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME Jul 15, 2020 Abandoned
Array ( [id] => 17359869 [patent_doc_number] => 20220020665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => DOUBLE-SIDE BACK-END-OF-LINE METALLIZATION FOR PSEUDO THROUGH-SILICON VIA INTEGRATION [patent_app_type] => utility [patent_app_number] => 16/928759 [patent_app_country] => US [patent_app_date] => 2020-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16928759 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/928759
DOUBLE-SIDE BACK-END-OF-LINE METALLIZATION FOR PSEUDO THROUGH-SILICON VIA INTEGRATION Jul 13, 2020 Abandoned
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