Search

Phat X. Cao

Examiner (ID: 7067)

Most Active Art Unit
2814
Art Unit(s)
2508, 2817, 2814
Total Applications
1687
Issued Applications
1251
Pending Applications
92
Abandoned Applications
373

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16402499 [patent_doc_number] => 20200343357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => Method for Fabricating Metal Gate Devices and Resulting Structures [patent_app_type] => utility [patent_app_number] => 16/923867 [patent_app_country] => US [patent_app_date] => 2020-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16923867 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/923867
Method for fabricating metal gate devices and resulting structures Jul 7, 2020 Issued
Array ( [id] => 17188988 [patent_doc_number] => 20210335873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => PHOTOELECTRIC CONVERSION DEVICE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/962077 [patent_app_country] => US [patent_app_date] => 2020-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4660 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16962077 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/962077
PHOTOELECTRIC CONVERSION DEVICE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE Jul 2, 2020 Abandoned
Array ( [id] => 19733910 [patent_doc_number] => 12211912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Semiconductor device and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 16/968877 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 8440 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16968877 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/968877
Semiconductor device and fabrication method thereof Jun 29, 2020 Issued
Array ( [id] => 17855401 [patent_doc_number] => 20220285444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => DISPLAY PANEL AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/053186 [patent_app_country] => US [patent_app_date] => 2020-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17053186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/053186
Display panel and manufacturing method thereof Jun 23, 2020 Issued
Array ( [id] => 19016353 [patent_doc_number] => 11923295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Interconnect level with high resistance layer and method of forming the same [patent_app_type] => utility [patent_app_number] => 16/906659 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10263 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16906659 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/906659
Interconnect level with high resistance layer and method of forming the same Jun 18, 2020 Issued
Array ( [id] => 17295429 [patent_doc_number] => 20210391268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => MICROELECTRONIC STRUCTURES INCLUDING BRIDGES [patent_app_type] => utility [patent_app_number] => 16/902910 [patent_app_country] => US [patent_app_date] => 2020-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 41239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16902910 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/902910
Microelectronic structures including bridges Jun 15, 2020 Issued
Array ( [id] => 16858437 [patent_doc_number] => 20210159182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => Semiconductor Devices and Methods of Manufacture [patent_app_type] => utility [patent_app_number] => 16/900174 [patent_app_country] => US [patent_app_date] => 2020-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12583 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16900174 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/900174
Semiconductor Devices and Methods of Manufacture Jun 11, 2020 Pending
Array ( [id] => 17295477 [patent_doc_number] => 20210391316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => SEPARATION METHOD AND ASSEMBLY FOR CHIP-ON-WAFER PROCESSING [patent_app_type] => utility [patent_app_number] => 16/898180 [patent_app_country] => US [patent_app_date] => 2020-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3911 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16898180 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/898180
Separation method and assembly for chip-on-wafer processing Jun 9, 2020 Issued
Array ( [id] => 18688348 [patent_doc_number] => 11784091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Structure and formation method of chip package with fan-out feature [patent_app_type] => utility [patent_app_number] => 16/893939 [patent_app_country] => US [patent_app_date] => 2020-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 7522 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16893939 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/893939
Structure and formation method of chip package with fan-out feature Jun 4, 2020 Issued
Array ( [id] => 16316343 [patent_doc_number] => 20200295081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => DISPLAY DEVICES [patent_app_type] => utility [patent_app_number] => 16/890009 [patent_app_country] => US [patent_app_date] => 2020-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9399 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16890009 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/890009
Display devices Jun 1, 2020 Issued
Array ( [id] => 17115635 [patent_doc_number] => 20210296232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => STAIRCASE STRUCTURE IN THREE-DIMENSIONAL MEMORY DEVICE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/881339 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16881339 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/881339
Staircase structure in three-dimensional memory device and method for forming the same May 21, 2020 Issued
Array ( [id] => 19123556 [patent_doc_number] => 11967550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Semiconductor structure with via extending across adjacent conductive lines and method of forming the same [patent_app_type] => utility [patent_app_number] => 16/881000 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 57 [patent_no_of_words] => 11984 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16881000 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/881000
Semiconductor structure with via extending across adjacent conductive lines and method of forming the same May 21, 2020 Issued
Array ( [id] => 19341446 [patent_doc_number] => 12051643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Hybrid via interconnect structure [patent_app_type] => utility [patent_app_number] => 16/878043 [patent_app_country] => US [patent_app_date] => 2020-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 87 [patent_no_of_words] => 16912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16878043 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/878043
Hybrid via interconnect structure May 18, 2020 Issued
Array ( [id] => 16272487 [patent_doc_number] => 20200273975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => NITRIDE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 15/930070 [patent_app_country] => US [patent_app_date] => 2020-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15930070 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/930070
Nitride semiconductor device and fabrication method therefor May 11, 2020 Issued
Array ( [id] => 17122146 [patent_doc_number] => 11133288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => Semiconductor package including stacked semiconductor chips [patent_app_type] => utility [patent_app_number] => 15/930130 [patent_app_country] => US [patent_app_date] => 2020-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 10302 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15930130 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/930130
Semiconductor package including stacked semiconductor chips May 11, 2020 Issued
Array ( [id] => 17217822 [patent_doc_number] => 20210351160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => MITIGATING THERMAL IMPACTS ON ADJACENT STACKED SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/871490 [patent_app_country] => US [patent_app_date] => 2020-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4024 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16871490 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/871490
Mitigating thermal impacts on adjacent stacked semiconductor devices May 10, 2020 Issued
Array ( [id] => 16528764 [patent_doc_number] => 20200402845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/863007 [patent_app_country] => US [patent_app_date] => 2020-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6304 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16863007 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/863007
SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOF Apr 29, 2020 Abandoned
Array ( [id] => 16210691 [patent_doc_number] => 20200243681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => REDUCTION OF TOP SOURCE/DRAIN EXTERNAL RESISTANCE AND PARASITIC CAPACITANCE IN VERTICAL TRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/845350 [patent_app_country] => US [patent_app_date] => 2020-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16845350 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/845350
Reduction of top source/drain external resistance and parasitic capacitance in vertical transistors Apr 9, 2020 Issued
Array ( [id] => 16528861 [patent_doc_number] => 20200402942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/843860 [patent_app_country] => US [patent_app_date] => 2020-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21105 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16843860 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/843860
SEMICONDUCTOR STRUCTURE AND METHOD MANUFACTURING THE SAME Apr 7, 2020 Pending
Array ( [id] => 17130353 [patent_doc_number] => 20210305122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/835322 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6282 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16835322 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/835322
Semiconductor package and manufacturing method thereof Mar 30, 2020 Issued
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