Search

Phil K. Nguyen

Examiner (ID: 874, Phone: (571)270-3356 , Office: P/2118 )

Most Active Art Unit
2187
Art Unit(s)
2115, 2187, 2118, 2176
Total Applications
639
Issued Applications
514
Pending Applications
43
Abandoned Applications
95

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18832351 [patent_doc_number] => 20230400878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => SYNCHRONIZATION OF A CLOCK GENERATOR DIVIDER SETTING AND MULTIPLE INDEPENDENT COMPONENT CLOCK DIVIDER SETTINGS [patent_app_type] => utility [patent_app_number] => 18/240052 [patent_app_country] => US [patent_app_date] => 2023-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5984 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18240052 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/240052
Synchronization of a clock generator divider setting and multiple independent component clock divider settings Aug 29, 2023 Issued
Array ( [id] => 19492973 [patent_doc_number] => 12111684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die module [patent_app_type] => utility [patent_app_number] => 18/455101 [patent_app_country] => US [patent_app_date] => 2023-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6691 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18455101 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/455101
Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die module Aug 23, 2023 Issued
Array ( [id] => 20166471 [patent_doc_number] => 20250258518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => TRACK PLAN TO IMPROVE CLOCK SKEW [patent_app_type] => utility [patent_app_number] => 19/100846 [patent_app_country] => US [patent_app_date] => 2023-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1164 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19100846 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/100846
TRACK PLAN TO IMPROVE CLOCK SKEW Aug 15, 2023 Pending
Array ( [id] => 20166471 [patent_doc_number] => 20250258518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => TRACK PLAN TO IMPROVE CLOCK SKEW [patent_app_type] => utility [patent_app_number] => 19/100846 [patent_app_country] => US [patent_app_date] => 2023-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1164 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19100846 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/100846
TRACK PLAN TO IMPROVE CLOCK SKEW Aug 15, 2023 Pending
Array ( [id] => 18989518 [patent_doc_number] => 20240061487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => POWER LOSS PROTECTION USING THERMOELECTRIC GENERATOR [patent_app_type] => utility [patent_app_number] => 18/233594 [patent_app_country] => US [patent_app_date] => 2023-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7508 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18233594 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/233594
POWER LOSS PROTECTION USING THERMOELECTRIC GENERATOR Aug 13, 2023 Pending
Array ( [id] => 18989518 [patent_doc_number] => 20240061487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => POWER LOSS PROTECTION USING THERMOELECTRIC GENERATOR [patent_app_type] => utility [patent_app_number] => 18/233594 [patent_app_country] => US [patent_app_date] => 2023-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7508 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18233594 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/233594
POWER LOSS PROTECTION USING THERMOELECTRIC GENERATOR Aug 13, 2023 Pending
Array ( [id] => 19771762 [patent_doc_number] => 20250053188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => CONTROLLER, SYSTEM AND METHOD FOR CONTROLLING MEMORIES IN STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 18/231133 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4646 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18231133 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/231133
CONTROLLER, SYSTEM AND METHOD FOR CONTROLLING MEMORIES IN STORAGE DEVICES Aug 6, 2023 Pending
Array ( [id] => 19756260 [patent_doc_number] => 20250044825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => CIRCUIT AND METHODOLOGY FOR POWER PROFILE [patent_app_type] => utility [patent_app_number] => 18/365006 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365006 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/365006
Circuit and methodology for power profile Aug 2, 2023 Issued
Array ( [id] => 19756262 [patent_doc_number] => 20250044827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => MEASURING AND COMPENSATING FOR CLOCK TREE VARIATION [patent_app_type] => utility [patent_app_number] => 18/364336 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18364336 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/364336
Measuring and compensating for clock tree variation Aug 1, 2023 Issued
Array ( [id] => 19756262 [patent_doc_number] => 20250044827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => MEASURING AND COMPENSATING FOR CLOCK TREE VARIATION [patent_app_type] => utility [patent_app_number] => 18/364336 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18364336 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/364336
Measuring and compensating for clock tree variation Aug 1, 2023 Issued
Array ( [id] => 19204486 [patent_doc_number] => 20240176385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => APPARATUSES AND METHODS FOR TIMING SKEW CALIBRATION [patent_app_type] => utility [patent_app_number] => 18/363906 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363906 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/363906
Apparatuses and methods for timing skew calibration Aug 1, 2023 Issued
Array ( [id] => 18772535 [patent_doc_number] => 20230367361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => ASYNCHRONOUS ASIC [patent_app_type] => utility [patent_app_number] => 18/358623 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6847 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358623 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358623
Asynchronous ASIC Jul 24, 2023 Issued
Array ( [id] => 18925063 [patent_doc_number] => 20240028067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => TIME SYNCHRONIZATION BETWEEN A MASTER AND A SLAVE IN A NETWORK [patent_app_type] => utility [patent_app_number] => 18/223281 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 394 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18223281 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/223281
Time synchronization between a master and a slave in a network Jul 17, 2023 Issued
Array ( [id] => 19710988 [patent_doc_number] => 20250021130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => Clock synchronization monitoring system [patent_app_type] => utility [patent_app_number] => 18/349976 [patent_app_country] => US [patent_app_date] => 2023-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9537 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18349976 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/349976
Clock synchronization monitoring system Jul 10, 2023 Pending
Array ( [id] => 19466104 [patent_doc_number] => 20240319774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => ENERGY CONSUMPTION OPTIMIZATION IN DIGITAL TWIN APPLICATIONS [patent_app_type] => utility [patent_app_number] => 18/342780 [patent_app_country] => US [patent_app_date] => 2023-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10777 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18342780 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/342780
ENERGY CONSUMPTION OPTIMIZATION IN DIGITAL TWIN APPLICATIONS Jun 27, 2023 Pending
Array ( [id] => 19347021 [patent_doc_number] => 20240255984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => CLOCK ALIGNING CIRCUIT AND METHODS FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/322734 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18322734 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/322734
CLOCK ALIGNING CIRCUIT AND METHODS FOR OPERATING THE SAME May 23, 2023 Pending
Array ( [id] => 18651588 [patent_doc_number] => 20230297424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => SYSTEM, APPARATUS AND METHOD FOR PROVIDING HARDWARE STATE FEEDBACK TO AN OPERATING SYSTEM IN A HETEROGENEOUS PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/322636 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18322636 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/322636
System, apparatus and method for providing hardware state feedback to an operating system in a heterogeneous processor May 23, 2023 Issued
Array ( [id] => 18598865 [patent_doc_number] => 20230273664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => SYSTEMS AND METHODS FOR ELASTIC DELIVERY, PROCESSING, AND STORAGE FOR WEARABLE DEVICES BASED ON SYSTEM RESOURCES [patent_app_type] => utility [patent_app_number] => 18/312768 [patent_app_country] => US [patent_app_date] => 2023-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312768 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/312768
Systems and methods for elastic delivery, processing, and storage for wearable devices based on system resources May 4, 2023 Issued
Array ( [id] => 18981838 [patent_doc_number] => 11907010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Multi-clock synchronization in power grids [patent_app_type] => utility [patent_app_number] => 18/304404 [patent_app_country] => US [patent_app_date] => 2023-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4986 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18304404 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/304404
Multi-clock synchronization in power grids Apr 20, 2023 Issued
Array ( [id] => 19084637 [patent_doc_number] => 20240111438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => RELIABILITY ASSESSMENT FOR USE WITH POWER-PER-PROCESSING EVENT ESTIMATIONS WITHIN A DATA STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/132230 [patent_app_country] => US [patent_app_date] => 2023-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21739 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18132230 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/132230
RELIABILITY ASSESSMENT FOR USE WITH POWER-PER-PROCESSING EVENT ESTIMATIONS WITHIN A DATA STORAGE DEVICE Apr 6, 2023 Pending
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