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Philip A. Guyton

Examiner (ID: 3549)

Most Active Art Unit
2113
Art Unit(s)
2113
Total Applications
1056
Issued Applications
841
Pending Applications
57
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19161230 [patent_doc_number] => 20240153937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => INTERPOSER [patent_app_type] => utility [patent_app_number] => 18/417485 [patent_app_country] => US [patent_app_date] => 2024-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4443 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18417485 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/417485
INTERPOSER Jan 18, 2024 Pending
Array ( [id] => 19634589 [patent_doc_number] => 20240413038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => STACKED SEMICONDUCTOR PACKAGE AND LOWER SEMICONDUCTOR PACKAGE USED FOR THE SAME [patent_app_type] => utility [patent_app_number] => 18/402558 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15076 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402558 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/402558
STACKED SEMICONDUCTOR PACKAGE AND LOWER SEMICONDUCTOR PACKAGE USED FOR THE SAME Jan 1, 2024 Pending
Array ( [id] => 20055933 [patent_doc_number] => 20250194155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => NANOSHEET FET WITH EXPANDED GATE REGION [patent_app_type] => utility [patent_app_number] => 18/534093 [patent_app_country] => US [patent_app_date] => 2023-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3131 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18534093 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/534093
NANOSHEET FET WITH EXPANDED GATE REGION Dec 7, 2023 Pending
Array ( [id] => 19116419 [patent_doc_number] => 20240128169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/533721 [patent_app_country] => US [patent_app_date] => 2023-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8322 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18533721 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/533721
SEMICONDUCTOR DEVICE Dec 7, 2023 Pending
Array ( [id] => 19634764 [patent_doc_number] => 20240413213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => NOBLE FORMATION METHOD OF CMOS FOR 3D STACKED FET WITH BSPDN [patent_app_type] => utility [patent_app_number] => 18/378943 [patent_app_country] => US [patent_app_date] => 2023-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18378943 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/378943
NOBLE FORMATION METHOD OF CMOS FOR 3D STACKED FET WITH BSPDN Oct 10, 2023 Pending
Array ( [id] => 19146378 [patent_doc_number] => 20240145408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => CHIP WITH CRACK GUIDING STRUCTURE COMBINED WITH CRACK STOP STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/378858 [patent_app_country] => US [patent_app_date] => 2023-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11427 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18378858 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/378858
CHIP WITH CRACK GUIDING STRUCTURE COMBINED WITH CRACK STOP STRUCTURE Oct 10, 2023 Pending
Array ( [id] => 19116605 [patent_doc_number] => 20240128355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => SACRIFICIAL SOURCE/DRAIN FOR METALLIC SOURCE/DRAIN HORIZONTAL GATE ALL AROUND ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/378850 [patent_app_country] => US [patent_app_date] => 2023-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18378850 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/378850
SACRIFICIAL SOURCE/DRAIN FOR METALLIC SOURCE/DRAIN HORIZONTAL GATE ALL AROUND ARCHITECTURE Oct 10, 2023 Pending
Array ( [id] => 19206337 [patent_doc_number] => 20240178236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => DISPLAY DEVICE AND MANUFACTURING METHOD OF DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/378832 [patent_app_country] => US [patent_app_date] => 2023-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18378832 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/378832
DISPLAY DEVICE AND MANUFACTURING METHOD OF DISPLAY DEVICE Oct 10, 2023 Pending
Array ( [id] => 19751603 [patent_doc_number] => 20250040168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => SELF-ALIGNED GATE CONTACT OVER LOCALLY RAISED GATE [patent_app_type] => utility [patent_app_number] => 18/360856 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360856 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360856
SELF-ALIGNED GATE CONTACT OVER LOCALLY RAISED GATE Jul 27, 2023 Pending
Array ( [id] => 19038416 [patent_doc_number] => 20240088231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/226386 [patent_app_country] => US [patent_app_date] => 2023-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6035 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18226386 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/226386
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME Jul 25, 2023 Pending
Array ( [id] => 19751612 [patent_doc_number] => 20250040177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => Area Efficient Fin-Based Laterally-Diffused Metal-Oxide Semiconductor Field-Effect Transistor [patent_app_type] => utility [patent_app_number] => 18/359669 [patent_app_country] => US [patent_app_date] => 2023-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359669 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/359669
Area Efficient Fin-Based Laterally-Diffused Metal-Oxide Semiconductor Field-Effect Transistor Jul 25, 2023 Pending
Array ( [id] => 19751601 [patent_doc_number] => 20250040166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => Planar JFET Device with Reduced Gate Resistance [patent_app_type] => utility [patent_app_number] => 18/358367 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7479 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358367 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358367
Planar JFET Device with Reduced Gate Resistance Jul 24, 2023 Pending
Array ( [id] => 17988371 [patent_doc_number] => 20220354408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => BIOLOGICAL-ELECTRODE PROTECTION MODULES, MEDICAL DEVICES AND BIOLOGICAL IMPLANTS, AND THEIR FABRICATION METHODS [patent_app_type] => utility [patent_app_number] => 17/874668 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6467 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874668 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874668
BIOLOGICAL-ELECTRODE PROTECTION MODULES, MEDICAL DEVICES AND BIOLOGICAL IMPLANTS, AND THEIR FABRICATION METHODS Jul 26, 2022 Pending
Array ( [id] => 19054775 [patent_doc_number] => 20240096744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => SEMICONDUCTOR DEVICE AND INVERTER UNIT [patent_app_type] => utility [patent_app_number] => 18/551569 [patent_app_country] => US [patent_app_date] => 2021-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18551569 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/551569
SEMICONDUCTOR DEVICE AND INVERTER UNIT Aug 9, 2021 Pending
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