Search

Philip L. Cotey

Examiner (ID: 12874, Phone: (571)270-1029 , Office: P/2855 )

Most Active Art Unit
2855
Art Unit(s)
2855, 2856
Total Applications
844
Issued Applications
667
Pending Applications
70
Abandoned Applications
119

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18363882 [patent_doc_number] => 20230145473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => SEMICONDUCTOR ASSEMBLIES WITH REDISTRIBUTION STRUCTURES FOR DIE STACK SIGNAL ROUTING [patent_app_type] => utility [patent_app_number] => 18/094320 [patent_app_country] => US [patent_app_date] => 2023-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6582 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18094320 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/094320
Semiconductor assemblies with redistribution structures for die stack signal routing Jan 5, 2023 Issued
Array ( [id] => 18379778 [patent_doc_number] => 20230154867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => CHIP STRUCTURE AND SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/150866 [patent_app_country] => US [patent_app_date] => 2023-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18150866 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/150866
Chip structure and semiconductor structure comprising auxiliary bonding region above guard ring structure Jan 5, 2023 Issued
Array ( [id] => 18361790 [patent_doc_number] => 20230143381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/150541 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18150541 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/150541
Electronic device comprising a transferred portion of plurality of chips and method for manufacturing the same Jan 4, 2023 Issued
Array ( [id] => 18347938 [patent_doc_number] => 20230136049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/092922 [patent_app_country] => US [patent_app_date] => 2023-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6017 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18092922 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/092922
Semiconductor device package including multiple substrates with different functions Jan 2, 2023 Issued
Array ( [id] => 19023173 [patent_doc_number] => 20240079344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => PACKAGING ASSEMBLY FOR SEMICONDUCTOR DEVICE AND METHOD OF MAKING [patent_app_type] => utility [patent_app_number] => 18/092852 [patent_app_country] => US [patent_app_date] => 2023-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18092852 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/092852
PACKAGING ASSEMBLY FOR SEMICONDUCTOR DEVICE AND METHOD OF MAKING Jan 2, 2023 Abandoned
Array ( [id] => 20390812 [patent_doc_number] => 12490562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Display panel comprising multiple pixel structures including repaired pixel structure [patent_app_type] => utility [patent_app_number] => 18/088774 [patent_app_country] => US [patent_app_date] => 2022-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 40 [patent_no_of_words] => 3093 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18088774 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/088774
Display panel comprising multiple pixel structures including repaired pixel structure Dec 26, 2022 Issued
Array ( [id] => 18325745 [patent_doc_number] => 20230123873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => INTER-LEVEL CONNECTION FOR MULTI-LAYER STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/084292 [patent_app_country] => US [patent_app_date] => 2022-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18084292 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/084292
Inter-level connection for multi-layer structures Dec 18, 2022 Issued
Array ( [id] => 18456278 [patent_doc_number] => 20230197560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => THERMOELECTRIC COOLING IN MICROELECTRONICS [patent_app_type] => utility [patent_app_number] => 18/067668 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7647 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18067668 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/067668
THERMOELECTRIC COOLING IN MICROELECTRONICS Dec 15, 2022 Pending
Array ( [id] => 18540881 [patent_doc_number] => 20230245992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => INTEGRATED CIRCUIT CHIP PACKAGE THAT DOES NOT UTILIZE A LEADFRAME [patent_app_type] => utility [patent_app_number] => 18/081248 [patent_app_country] => US [patent_app_date] => 2022-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3479 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18081248 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/081248
Integrated circuit chip package that does not utilize a leadframe Dec 13, 2022 Issued
Array ( [id] => 18840221 [patent_doc_number] => 11848302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Chip package structure with ring-like structure [patent_app_type] => utility [patent_app_number] => 18/065156 [patent_app_country] => US [patent_app_date] => 2022-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7969 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18065156 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/065156
Chip package structure with ring-like structure Dec 12, 2022 Issued
Array ( [id] => 19046689 [patent_doc_number] => 11935809 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Semiconductor package thermal spreader having integrated EF/EMI shielding and antenna elements [patent_app_type] => utility [patent_app_number] => 18/064607 [patent_app_country] => US [patent_app_date] => 2022-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 5506 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18064607 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/064607
Semiconductor package thermal spreader having integrated EF/EMI shielding and antenna elements Dec 11, 2022 Issued
Array ( [id] => 20748329 [patent_doc_number] => 12648270 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-02 [patent_title] => Light-emitting device and manufacturing method thereof, taillight and vehicle [patent_app_type] => utility [patent_app_number] => 18/278229 [patent_app_country] => US [patent_app_date] => 2022-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 3299 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18278229 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/278229
Light-emitting device and manufacturing method thereof, taillight and vehicle Nov 28, 2022 Issued
Array ( [id] => 20132311 [patent_doc_number] => 12374629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Electromagnetic interference shielding package structure, manufacturing method thereof, and electronic assembly [patent_app_type] => utility [patent_app_number] => 17/988844 [patent_app_country] => US [patent_app_date] => 2022-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17988844 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/988844
Electromagnetic interference shielding package structure, manufacturing method thereof, and electronic assembly Nov 16, 2022 Issued
Array ( [id] => 20760253 [patent_doc_number] => 12653048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-09 [patent_title] => Double side molded land grid array package platform using a substrate with copper posts [patent_app_type] => utility [patent_app_number] => 17/989559 [patent_app_country] => US [patent_app_date] => 2022-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17989559 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/989559
Double side molded land grid array package platform using a substrate with copper posts Nov 16, 2022 Issued
Array ( [id] => 20292965 [patent_doc_number] => 20250318208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => TUNNELING FIELD EFFECT TRANSISTOR HAVING BURIED DRAIN STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/713881 [patent_app_country] => US [patent_app_date] => 2022-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18713881 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/713881
TUNNELING FIELD EFFECT TRANSISTOR HAVING BURIED DRAIN STRUCTURE Nov 14, 2022 Pending
Array ( [id] => 19183781 [patent_doc_number] => 11990381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Integrated circuit packages having support rings [patent_app_type] => utility [patent_app_number] => 17/986498 [patent_app_country] => US [patent_app_date] => 2022-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8799 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17986498 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/986498
Integrated circuit packages having support rings Nov 13, 2022 Issued
Array ( [id] => 18242659 [patent_doc_number] => 20230074970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => SACRIFICIAL REDISTRIBUTION LAYER IN MICROELECTRONIC ASSEMBLIES HAVING DIRECT BONDING [patent_app_type] => utility [patent_app_number] => 18/053869 [patent_app_country] => US [patent_app_date] => 2022-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18053869 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/053869
Sacrificial redistribution layer in microelectronic assemblies having direct bonding Nov 8, 2022 Issued
Array ( [id] => 18195607 [patent_doc_number] => 20230049126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => CHIP PACKAGE [patent_app_type] => utility [patent_app_number] => 17/980507 [patent_app_country] => US [patent_app_date] => 2022-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17980507 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/980507
Chip package including substrate having through hole and redistribution line Nov 2, 2022 Issued
Array ( [id] => 18891090 [patent_doc_number] => 11869868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Multi-segment wire-bond [patent_app_type] => utility [patent_app_number] => 18/051571 [patent_app_country] => US [patent_app_date] => 2022-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18051571 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/051571
Multi-segment wire-bond Oct 31, 2022 Issued
Array ( [id] => 18207593 [patent_doc_number] => 20230053850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/046224 [patent_app_country] => US [patent_app_date] => 2022-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7966 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18046224 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/046224
Package structure comprising conductive metal board and ground element Oct 12, 2022 Issued
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