Search

Philip S. Hyder

Examiner (ID: 13638, Phone: (571)272-2621 , Office: P/2917 )

Most Active Art Unit
2917
Art Unit(s)
2917, 2924, 2900, 2902, 2913, 2912, 2915
Total Applications
8384
Issued Applications
8127
Pending Applications
88
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20692158 [patent_doc_number] => 12622334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => Semiconductor module [patent_app_type] => utility [patent_app_number] => 19/304208 [patent_app_country] => US [patent_app_date] => 2025-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 25851 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 458 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19304208 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/304208
Semiconductor module Aug 18, 2025 Issued
Array ( [id] => 20399055 [patent_doc_number] => 20250374530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => BIT LINE CONTACT STRUCTURE, SEMICONDUCTOR DEVICE WITH CONTACT-ISOLATING SPACERS, AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/741175 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6639 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741175 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741175
BIT LINE CONTACT STRUCTURE, SEMICONDUCTOR DEVICE WITH CONTACT-ISOLATING SPACERS, AND METHOD FOR FABRICATING THE SAME Jun 11, 2024 Pending
Array ( [id] => 19468164 [patent_doc_number] => 20240321834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/734915 [patent_app_country] => US [patent_app_date] => 2024-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11701 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18734915 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/734915
SEMICONDUCTOR DEVICE Jun 4, 2024 Pending
Array ( [id] => 20399054 [patent_doc_number] => 20250374529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => BIT LINE CONTACT STRUCTURE, SEMICONDUCTOR DEVICE WITH CONTACT-ISOLATING SPACERS, AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/676829 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6639 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18676829 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/676829
BIT LINE CONTACT STRUCTURE, SEMICONDUCTOR DEVICE WITH CONTACT-ISOLATING SPACERS, AND METHOD FOR FABRICATING THE SAME May 28, 2024 Pending
Array ( [id] => 20399194 [patent_doc_number] => 20250374669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/677191 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677191 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677191
INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME May 28, 2024 Pending
Array ( [id] => 20381918 [patent_doc_number] => 20250364411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => ELECTRONIC DEVICES AND METHODS OF MANUFACTURING ELECTRONIC DEVICES [patent_app_type] => utility [patent_app_number] => 18/671474 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5454 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18671474 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/671474
ELECTRONIC DEVICES AND METHODS OF MANUFACTURING ELECTRONIC DEVICES May 21, 2024 Pending
Array ( [id] => 19773396 [patent_doc_number] => 20250054822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/654799 [patent_app_country] => US [patent_app_date] => 2024-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18654799 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/654799
INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME May 2, 2024 Pending
Array ( [id] => 19384700 [patent_doc_number] => 20240274570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => STUD BUMP FOR WIREBONDING HIGH VOLTAGE ISOLATION BARRIER CONNECTION [patent_app_type] => utility [patent_app_number] => 18/648632 [patent_app_country] => US [patent_app_date] => 2024-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4542 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18648632 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/648632
STUD BUMP FOR WIREBONDING HIGH VOLTAGE ISOLATION BARRIER CONNECTION Apr 28, 2024 Pending
Array ( [id] => 20324717 [patent_doc_number] => 20250336805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => THROUGH LAYER SKIP VIA [patent_app_type] => utility [patent_app_number] => 18/644971 [patent_app_country] => US [patent_app_date] => 2024-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18644971 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/644971
THROUGH LAYER SKIP VIA Apr 23, 2024 Pending
Array ( [id] => 19364227 [patent_doc_number] => 20240266261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/637032 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 84720 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637032 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/637032
SEMICONDUCTOR DEVICE Apr 15, 2024 Pending
Array ( [id] => 19823276 [patent_doc_number] => 20250081483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 18/636601 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18636601 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/636601
INTEGRATED CIRCUIT DEVICE Apr 15, 2024 Pending
Array ( [id] => 20233746 [patent_doc_number] => 20250291065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => METHOD AND APPARATUS TO RETROFIT LEGACY GLOBAL POSITIONING SATELLITE (GPS) AND OTHER GLOBAL NAVIGATION SATELLITE SYSTEM (GNSS) RECEIVERS [patent_app_type] => utility [patent_app_number] => 18/635435 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635435 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635435
METHOD AND APPARATUS TO RETROFIT LEGACY GLOBAL POSITIONING SATELLITE (GPS) AND OTHER GLOBAL NAVIGATION SATELLITE SYSTEM (GNSS) RECEIVERS Apr 14, 2024 Pending
Array ( [id] => 19349252 [patent_doc_number] => 20240258216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => Power Module with Semiconductor Packages Mounted on Metal Frame [patent_app_type] => utility [patent_app_number] => 18/631335 [patent_app_country] => US [patent_app_date] => 2024-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18631335 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/631335
Power Module with Semiconductor Packages Mounted on Metal Frame Apr 9, 2024 Pending
Array ( [id] => 19500546 [patent_doc_number] => 20240339564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/625617 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625617 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625617
SEMICONDUCTOR DEVICE Apr 2, 2024 Pending
Array ( [id] => 19362057 [patent_doc_number] => 20240264091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => METHOD FOR INSPECTING VIA HOLE OF WAFER [patent_app_type] => utility [patent_app_number] => 18/624040 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624040 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/624040
METHOD FOR INSPECTING VIA HOLE OF WAFER Mar 31, 2024 Pending
Array ( [id] => 20283667 [patent_doc_number] => 20250308909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => METHOD OF MAKING SILICIDE IN HIGH-ASPECT RATIO STRUCTURES BY H-RADICAL ASSISTED PROCESSES [patent_app_type] => utility [patent_app_number] => 18/623546 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623546 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/623546
METHOD OF MAKING SILICIDE IN HIGH-ASPECT RATIO STRUCTURES BY H-RADICAL ASSISTED PROCESSES Mar 31, 2024 Pending
Array ( [id] => 19532061 [patent_doc_number] => 20240355963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => LIGHT-EMITTING DIODE AND LIGHT-EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 18/621149 [patent_app_country] => US [patent_app_date] => 2024-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18621149 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/621149
LIGHT-EMITTING DIODE AND LIGHT-EMITTING DEVICE Mar 28, 2024 Pending
Array ( [id] => 20028843 [patent_doc_number] => 20250167065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => SEMICONDUCTOR PACKAGE INCLUDING HEAT DISSIPATION MEMBER, AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/617147 [patent_app_country] => US [patent_app_date] => 2024-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18617147 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/617147
SEMICONDUCTOR PACKAGE INCLUDING HEAT DISSIPATION MEMBER, AND METHOD FOR MANUFACTURING THE SAME Mar 25, 2024 Pending
Array ( [id] => 19468335 [patent_doc_number] => 20240322005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => METHOD FOR MAKING NANOSTRUCTURE TRANSISTORS WITH OFFSET SOURCE/DRAIN DOPANT BLOCKING STRUCTURES INCLUDING A SUPERLATTICE [patent_app_type] => utility [patent_app_number] => 18/613356 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4997 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18613356 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/613356
Method for making nanostructure transistors with offset source/drain dopant blocking structures including a superlattice Mar 21, 2024 Issued
Array ( [id] => 20252922 [patent_doc_number] => 20250301791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => SEMICONDUCTOR DEVICE WITH DIELECTRIC THERMAL CONDUCTOR [patent_app_type] => utility [patent_app_number] => 18/610973 [patent_app_country] => US [patent_app_date] => 2024-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610973 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/610973
SEMICONDUCTOR DEVICE WITH DIELECTRIC THERMAL CONDUCTOR Mar 19, 2024 Pending
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