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Philippe Derakshani

Examiner (ID: 5991)

Most Active Art Unit
3754
Art Unit(s)
3754, 3108, 3752, 3104
Total Applications
1621
Issued Applications
1361
Pending Applications
118
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17674952 [patent_doc_number] => 20220188119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => IDENTIFYING DEPENDENCIES IN A CONTROL SEQUENCE FOR EXECUTION ON A HARDWARE ACCELERATOR [patent_app_type] => utility [patent_app_number] => 17/119251 [patent_app_country] => US [patent_app_date] => 2020-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5376 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17119251 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/119251
Identifying dependencies in a control sequence for execution on a hardware accelerator Dec 10, 2020 Issued
Array ( [id] => 17572999 [patent_doc_number] => 11321269 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-03 [patent_title] => Dynamic address allocation in improved inter-integrated circuit communication [patent_app_type] => utility [patent_app_number] => 17/247391 [patent_app_country] => US [patent_app_date] => 2020-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 9224 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17247391 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/247391
Dynamic address allocation in improved inter-integrated circuit communication Dec 8, 2020 Issued
Array ( [id] => 16872281 [patent_doc_number] => 20210165748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => COMPUTER-IMPLEMENTED METHOD FOR INTEGRATING AT LEAST ONE SIGNAL VALUE INTO A VIRTUAL CONTROL UNIT [patent_app_type] => utility [patent_app_number] => 17/109785 [patent_app_country] => US [patent_app_date] => 2020-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5557 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17109785 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/109785
Computer-implemented method for integrating at least one signal value into a virtual control unit Dec 1, 2020 Issued
Array ( [id] => 16903194 [patent_doc_number] => 20210182110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => SYSTEM, BOARD CARD AND ELECTRONIC DEVICE FOR DATA ACCELERATED PROCESSING [patent_app_type] => utility [patent_app_number] => 17/108753 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7588 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108753 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/108753
System, board card and electronic device for data accelerated processing Nov 30, 2020 Issued
Array ( [id] => 17309146 [patent_doc_number] => 11210259 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-12-28 [patent_title] => Module for asynchronous differential serial communication [patent_app_type] => utility [patent_app_number] => 17/107254 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 8979 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 391 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107254 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107254
Module for asynchronous differential serial communication Nov 29, 2020 Issued
Array ( [id] => 17288337 [patent_doc_number] => 11204887 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-12-21 [patent_title] => Methods and systems for using UART and single wire protocols [patent_app_type] => utility [patent_app_number] => 17/103117 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4053 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103117 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103117
Methods and systems for using UART and single wire protocols Nov 23, 2020 Issued
Array ( [id] => 16856847 [patent_doc_number] => 20210157592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => REGISTER-PROVIDED-OPCODE INSTRUCTION [patent_app_type] => utility [patent_app_number] => 17/096014 [patent_app_country] => US [patent_app_date] => 2020-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13119 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17096014 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/096014
Register-provided-opcode instruction Nov 11, 2020 Issued
Array ( [id] => 17209578 [patent_doc_number] => 11169951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Distributed multi-die protocol application interface [patent_app_type] => utility [patent_app_number] => 17/096896 [patent_app_country] => US [patent_app_date] => 2020-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4819 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17096896 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/096896
Distributed multi-die protocol application interface Nov 11, 2020 Issued
Array ( [id] => 19356083 [patent_doc_number] => 12056531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Method and apparatus for accelerating convolutional neural network [patent_app_type] => utility [patent_app_number] => 18/015308 [patent_app_country] => US [patent_app_date] => 2020-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5633 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18015308 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/015308
Method and apparatus for accelerating convolutional neural network Nov 2, 2020 Issued
Array ( [id] => 17581105 [patent_doc_number] => 20220137960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => SYSTEM AND METHOD FOR PROCESSING LARGE DATASETS [patent_app_type] => utility [patent_app_number] => 17/087203 [patent_app_country] => US [patent_app_date] => 2020-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5049 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087203 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/087203
System and method for processing large datasets Nov 1, 2020 Issued
Array ( [id] => 17907405 [patent_doc_number] => 11461259 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Systems and methods for load detection on serial communication data lines [patent_app_type] => utility [patent_app_number] => 17/077696 [patent_app_country] => US [patent_app_date] => 2020-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7328 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17077696 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/077696
Systems and methods for load detection on serial communication data lines Oct 21, 2020 Issued
Array ( [id] => 17786410 [patent_doc_number] => 11409533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Pipeline merging in a circuit [patent_app_type] => utility [patent_app_number] => 17/074716 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 13542 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17074716 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/074716
Pipeline merging in a circuit Oct 19, 2020 Issued
Array ( [id] => 18052977 [patent_doc_number] => 11526361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-13 [patent_title] => Variable pipeline length in a barrel-multithreaded processor [patent_app_type] => utility [patent_app_number] => 17/074722 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 13449 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17074722 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/074722
Variable pipeline length in a barrel-multithreaded processor Oct 19, 2020 Issued
Array ( [id] => 17744444 [patent_doc_number] => 11392513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Graph-based data flow control system [patent_app_type] => utility [patent_app_number] => 17/071036 [patent_app_country] => US [patent_app_date] => 2020-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 14270 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17071036 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/071036
Graph-based data flow control system Oct 14, 2020 Issued
Array ( [id] => 16600237 [patent_doc_number] => 20210026768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => VIRTUAL NETWORK PRE-ARBITRATION FOR DEADLOCK AVOIDANCE AND ENHANCED PERFORMANCE [patent_app_type] => utility [patent_app_number] => 17/066650 [patent_app_country] => US [patent_app_date] => 2020-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25318 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17066650 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/066650
Virtual network pre-arbitration for deadlock avoidance and enhanced performance Oct 8, 2020 Issued
Array ( [id] => 18750559 [patent_doc_number] => 11809873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Selective use of branch prediction hints [patent_app_type] => utility [patent_app_number] => 17/033749 [patent_app_country] => US [patent_app_date] => 2020-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7164 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033749 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/033749
Selective use of branch prediction hints Sep 25, 2020 Issued
Array ( [id] => 16802162 [patent_doc_number] => 10997106 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-04 [patent_title] => Inter-smartNIC virtual-link for control and datapath connectivity [patent_app_type] => utility [patent_app_number] => 17/028242 [patent_app_country] => US [patent_app_date] => 2020-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 17241 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17028242 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/028242
Inter-smartNIC virtual-link for control and datapath connectivity Sep 21, 2020 Issued
Array ( [id] => 16722173 [patent_doc_number] => 20210089320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => DYNAMIC ASSIGNMENT OF SPECIAL TASKS IN DISTRIBUTED NETWORKS [patent_app_type] => utility [patent_app_number] => 17/020470 [patent_app_country] => US [patent_app_date] => 2020-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5651 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17020470 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/020470
Dynamic assignment of special tasks in distributed networks Sep 13, 2020 Issued
Array ( [id] => 16729862 [patent_doc_number] => 20210097009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => APPARATUS AND METHOD FOR BURST MODE DATA STORAGE [patent_app_type] => utility [patent_app_number] => 17/017252 [patent_app_country] => US [patent_app_date] => 2020-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17017252 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/017252
Apparatus and method for burst mode data storage Sep 9, 2020 Issued
Array ( [id] => 17331513 [patent_doc_number] => 11221977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Daisy chain mode entry sequence [patent_app_type] => utility [patent_app_number] => 16/998050 [patent_app_country] => US [patent_app_date] => 2020-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 11096 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16998050 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/998050
Daisy chain mode entry sequence Aug 19, 2020 Issued
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