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Philippe Derakshani

Examiner (ID: 5991)

Most Active Art Unit
3754
Art Unit(s)
3754, 3108, 3752, 3104
Total Applications
1621
Issued Applications
1361
Pending Applications
118
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20117468 [patent_doc_number] => 12367174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Non-homogeneous chiplets [patent_app_type] => utility [patent_app_number] => 18/680752 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18680752 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/680752
Non-homogeneous chiplets May 30, 2024 Issued
Array ( [id] => 20648473 [patent_doc_number] => 12603428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-14 [patent_title] => Information handling system dongle with orthogonal radiating antenna planes [patent_app_type] => utility [patent_app_number] => 18/676750 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 2429 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18676750 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/676750
Information handling system dongle with orthogonal radiating antenna planes May 28, 2024 Issued
Array ( [id] => 19545144 [patent_doc_number] => 20240362180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUCT ACCUMULATE INSTRUCTION FOR HYBRID FLOATING POINT FORMAT [patent_app_type] => utility [patent_app_number] => 18/647549 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 40560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647549 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647549
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUCT ACCUMULATE INSTRUCTION FOR HYBRID FLOATING POINT FORMAT Apr 25, 2024 Pending
Array ( [id] => 20415642 [patent_doc_number] => 12498927 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-12-16 [patent_title] => Microprocessor that allows same-fetch block start address co-residence of unrolled loop multi-fetch block macro-op cache entry and loop body macro-op cache entry used to build same [patent_app_type] => utility [patent_app_number] => 18/645281 [patent_app_country] => US [patent_app_date] => 2024-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 58 [patent_no_of_words] => 83869 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18645281 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/645281
Microprocessor that allows same-fetch block start address co-residence of unrolled loop multi-fetch block macro-op cache entry and loop body macro-op cache entry used to build same Apr 23, 2024 Issued
Array ( [id] => 20415643 [patent_doc_number] => 12498928 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-12-16 [patent_title] => Microprocessor that builds multi-fetch block macro-op cache entries in two-stage process [patent_app_type] => utility [patent_app_number] => 18/645274 [patent_app_country] => US [patent_app_date] => 2024-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 58 [patent_no_of_words] => 83881 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18645274 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/645274
Microprocessor that builds multi-fetch block macro-op cache entries in two-stage process Apr 23, 2024 Issued
Array ( [id] => 20415641 [patent_doc_number] => 12498926 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-12-16 [patent_title] => Microprocessor that builds consistent loop iteration count unrolled loop multi-fetch block macro-op cache entries [patent_app_type] => utility [patent_app_number] => 18/645260 [patent_app_country] => US [patent_app_date] => 2024-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 58 [patent_no_of_words] => 83206 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18645260 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/645260
Microprocessor that builds consistent loop iteration count unrolled loop multi-fetch block macro-op cache entries Apr 23, 2024 Issued
Array ( [id] => 20296659 [patent_doc_number] => 20250321902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => Symmetrical Control of Hardware Peripherals [patent_app_type] => utility [patent_app_number] => 18/636351 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18636351 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/636351
Symmetrical Control of Hardware Peripherals Apr 15, 2024 Pending
Array ( [id] => 20290145 [patent_doc_number] => 20250315388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => COORDINATED SET PERIPHERAL DEVICE PAIRING AND CONNECTION MANAGEMENT [patent_app_type] => utility [patent_app_number] => 18/629137 [patent_app_country] => US [patent_app_date] => 2024-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4538 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629137 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/629137
Coordinated set peripheral device pairing and connection management Apr 7, 2024 Issued
Array ( [id] => 19725903 [patent_doc_number] => 20250028654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => SYSTEM AND METHODS FOR AUTO-BAUD DETECTION [patent_app_type] => utility [patent_app_number] => 18/625332 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625332 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625332
System and methods for auto-baud detection Apr 2, 2024 Issued
Array ( [id] => 20281694 [patent_doc_number] => 20250306936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => DATA PACKING FOR POWER AND AREA-EFFICIENT MEMORY STRUCTURES AND PERFORMANCE-EFFICIENT DECODING OF ENCODED DATA [patent_app_type] => utility [patent_app_number] => 18/616932 [patent_app_country] => US [patent_app_date] => 2024-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11998 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18616932 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/616932
Data packing for power and area-efficient memory structures and performance-efficient decoding of encoded data Mar 25, 2024 Issued
Array ( [id] => 20249750 [patent_doc_number] => 20250298619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => INSTRUCTION SET ARCHITECTURE PUSH WITH FRAME POINTER INSTRUCTION [patent_app_type] => utility [patent_app_number] => 18/612737 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18612737 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/612737
Instruction set architecture push with frame pointer instruction Mar 20, 2024 Issued
Array ( [id] => 19787395 [patent_doc_number] => 20250061074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => COMPUTER COMMUNICATION DEVICE WITH INTER-DEVICE DATA COPYING [patent_app_type] => utility [patent_app_number] => 18/612360 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18612360 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/612360
Computer communication device with inter-device data copying Mar 20, 2024 Issued
Array ( [id] => 20249749 [patent_doc_number] => 20250298618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => TECHNIQUE FOR CONTROLLING STASHING OF DATA [patent_app_type] => utility [patent_app_number] => 18/610064 [patent_app_country] => US [patent_app_date] => 2024-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14102 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610064 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/610064
Technique for controlling stashing of data Mar 18, 2024 Issued
Array ( [id] => 20249748 [patent_doc_number] => 20250298617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => TECHNIQUE FOR CONTROLLING STASHING OF DATA [patent_app_type] => utility [patent_app_number] => 18/609654 [patent_app_country] => US [patent_app_date] => 2024-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18609654 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/609654
Technique for controlling stashing of data Mar 18, 2024 Issued
Array ( [id] => 20202992 [patent_doc_number] => 12405770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Matrix transpose and multiply [patent_app_type] => utility [patent_app_number] => 18/607024 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 48 [patent_no_of_words] => 21987 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18607024 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/607024
Matrix transpose and multiply Mar 14, 2024 Issued
Array ( [id] => 19756487 [patent_doc_number] => 20250045052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => METHODS AND APPARATUS TO SEQUENCE BRANCH OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/587432 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30743 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587432 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587432
METHODS AND APPARATUS TO SEQUENCE BRANCH OPERATIONS Feb 25, 2024 Issued
Array ( [id] => 19942588 [patent_doc_number] => 12314720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Look-up table write [patent_app_type] => utility [patent_app_number] => 18/436652 [patent_app_country] => US [patent_app_date] => 2024-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 40 [patent_no_of_words] => 19520 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18436652 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/436652
Look-up table write Feb 7, 2024 Issued
Array ( [id] => 19934882 [patent_doc_number] => 12308090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters [patent_app_type] => utility [patent_app_number] => 18/403480 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 2253 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403480 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/403480
Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters Jan 2, 2024 Issued
Array ( [id] => 19872963 [patent_doc_number] => 12265826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Systems for performing instructions to quickly convert and use tiles as 1D vectors [patent_app_type] => utility [patent_app_number] => 18/399014 [patent_app_country] => US [patent_app_date] => 2023-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 46 [patent_no_of_words] => 27149 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399014 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/399014
Systems for performing instructions to quickly convert and use tiles as 1D vectors Dec 27, 2023 Issued
Array ( [id] => 19250998 [patent_doc_number] => 20240201988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => Rotating Data Blocks [patent_app_type] => utility [patent_app_number] => 18/543036 [patent_app_country] => US [patent_app_date] => 2023-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10481 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18543036 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/543036
Rotating data blocks Dec 17, 2023 Issued
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