Search

Phillip A. Gray

Examiner (ID: 99, Phone: (571)272-7180 , Office: P/3763 )

Most Active Art Unit
3783
Art Unit(s)
3783, 3767, 3763
Total Applications
1197
Issued Applications
809
Pending Applications
95
Abandoned Applications
312

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20281522 [patent_doc_number] => 20250306764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => ENABLING MULTIPLE PHYSICAL LAYER CONFIGURATION OF MEMORY SUB-SYSTEM WITH MULTIPLE PORTS H [patent_app_type] => utility [patent_app_number] => 19/069834 [patent_app_country] => US [patent_app_date] => 2025-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19069834 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/069834
ENABLING MULTIPLE PHYSICAL LAYER CONFIGURATION OF MEMORY SUB-SYSTEM WITH MULTIPLE PORTS H Mar 3, 2025 Pending
Array ( [id] => 20017860 [patent_doc_number] => 20250156082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => WEAR LEVELING IN SOLID STATE DRIVES [patent_app_type] => utility [patent_app_number] => 19/022147 [patent_app_country] => US [patent_app_date] => 2025-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1131 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19022147 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/022147
WEAR LEVELING IN SOLID STATE DRIVES Jan 14, 2025 Pending
Array ( [id] => 19985743 [patent_doc_number] => 20250123965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => MULTI-LEVEL CACHE SYSTEM FOR REDUCTION OF STORAGE COSTS [patent_app_type] => utility [patent_app_number] => 19/002228 [patent_app_country] => US [patent_app_date] => 2024-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3839 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19002228 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/002228
MULTI-LEVEL CACHE SYSTEM FOR REDUCTION OF STORAGE COSTS Dec 25, 2024 Pending
Array ( [id] => 20095132 [patent_doc_number] => 20250225068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => PROCESSING SYSTEM, AND RELATED METHOD [patent_app_type] => utility [patent_app_number] => 18/937579 [patent_app_country] => US [patent_app_date] => 2024-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 460 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18937579 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/937579
PROCESSING SYSTEM, AND RELATED METHOD Nov 4, 2024 Pending
Array ( [id] => 20481668 [patent_doc_number] => 12530143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Storage device and operating method thereof [patent_app_type] => utility [patent_app_number] => 18/798819 [patent_app_country] => US [patent_app_date] => 2024-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 8394 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18798819 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/798819
Storage device and operating method thereof Aug 8, 2024 Issued
Array ( [id] => 20428355 [patent_doc_number] => 20250390447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-25 [patent_title] => Sideband Architecture For Power And Performance Subchannel And Channel-aware memory Controller Scheduling [patent_app_type] => utility [patent_app_number] => 18/748173 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11156 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18748173 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/748173
Sideband Architecture For Power And Performance Subchannel And Channel-aware memory Controller Scheduling Jun 19, 2024 Pending
Array ( [id] => 20537479 [patent_doc_number] => 12554556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Resource elimination method, apparatus, electronic device and readable storage medium [patent_app_type] => utility [patent_app_number] => 18/748075 [patent_app_country] => US [patent_app_date] => 2024-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18748075 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/748075
Resource elimination method, apparatus, electronic device and readable storage medium Jun 18, 2024 Issued
Array ( [id] => 19466484 [patent_doc_number] => 20240320154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => MULTI-LEVEL CACHE SECURITY [patent_app_type] => utility [patent_app_number] => 18/733125 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733125 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733125
Multi-level cache security Jun 3, 2024 Issued
Array ( [id] => 20257908 [patent_doc_number] => 12430258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Padding cached data with valid data for memory flush commands [patent_app_type] => utility [patent_app_number] => 18/672645 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4031 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672645 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672645
Padding cached data with valid data for memory flush commands May 22, 2024 Issued
Array ( [id] => 19391514 [patent_doc_number] => 20240281384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => MEMORY STORAGE DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/646226 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646226 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/646226
MEMORY STORAGE DEVICE AND METHOD Apr 24, 2024 Pending
Array ( [id] => 19588413 [patent_doc_number] => 20240385970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => METHODS, SYSTEMS, ARTICLES OF MANUFACTURE AND APPARATUS TO CONTROL ADDRESS SPACE ISOLATION IN A VIRTUAL MACHINE [patent_app_type] => utility [patent_app_number] => 18/625880 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625880 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625880
Methods, systems, articles of manufacture and apparatus to control address space isolation in a virtual machine Apr 2, 2024 Issued
Array ( [id] => 19856979 [patent_doc_number] => 12259813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Controller for controlling non-volatile semiconductor memory and method of controlling non-volatile semiconductor memory [patent_app_type] => utility [patent_app_number] => 18/624930 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 48 [patent_no_of_words] => 37425 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624930 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/624930
Controller for controlling non-volatile semiconductor memory and method of controlling non-volatile semiconductor memory Apr 1, 2024 Issued
Array ( [id] => 20537563 [patent_doc_number] => 12554640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based system [patent_app_type] => utility [patent_app_number] => 18/623366 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1088 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623366 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/623366
Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based system Mar 31, 2024 Issued
Array ( [id] => 20249887 [patent_doc_number] => 20250298756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => METHOD AND APPARATUS FOR SCALABLE EXCLUSIVE ACCESS MANAGEMENT IN MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/610080 [patent_app_country] => US [patent_app_date] => 2024-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610080 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/610080
METHOD AND APPARATUS FOR SCALABLE EXCLUSIVE ACCESS MANAGEMENT IN MEMORY SYSTEMS Mar 18, 2024 Pending
Array ( [id] => 19660648 [patent_doc_number] => 20240427713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => STORAGE APPARATUS AND CONTROL METHOD FOR STORAGE APPARATUS [patent_app_type] => utility [patent_app_number] => 18/599738 [patent_app_country] => US [patent_app_date] => 2024-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 536 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18599738 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/599738
Storage apparatus and control method for storage apparatus Mar 7, 2024 Issued
Array ( [id] => 20434228 [patent_doc_number] => 12504915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-23 [patent_title] => Performing memory access operations based on quad-level cell to single-level cell mapping table [patent_app_type] => utility [patent_app_number] => 18/433688 [patent_app_country] => US [patent_app_date] => 2024-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3950 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18433688 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/433688
Performing memory access operations based on quad-level cell to single-level cell mapping table Feb 5, 2024 Issued
Array ( [id] => 20580031 [patent_doc_number] => 12572281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Adaptive die selection for block family scan [patent_app_type] => utility [patent_app_number] => 18/403255 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4825 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403255 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/403255
Adaptive die selection for block family scan Jan 2, 2024 Issued
Array ( [id] => 19220000 [patent_doc_number] => 20240184704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => METHOD AND APPARATUS FOR READING CACHE DATA, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/524706 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9756 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524706 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/524706
METHOD AND APPARATUS FOR READING CACHE DATA, AND STORAGE MEDIUM Nov 29, 2023 Pending
Array ( [id] => 20331583 [patent_doc_number] => 12461860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Physical address based set partitioning [patent_app_type] => utility [patent_app_number] => 18/522049 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 16803 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18522049 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/522049
Physical address based set partitioning Nov 27, 2023 Issued
Array ( [id] => 20027180 [patent_doc_number] => 20250165402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => Memory-Access Policies in Peripheral Device based on Memory Usage Characteristics [patent_app_type] => utility [patent_app_number] => 18/513563 [patent_app_country] => US [patent_app_date] => 2023-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1077 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513563 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/513563
Memory-Access Policies in Peripheral Device based on Memory Usage Characteristics Nov 18, 2023 Pending
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