Search

Phillip J Groutt

Examiner (ID: 11154)

Most Active Art Unit
2761
Art Unit(s)
2411, 2761
Total Applications
50
Issued Applications
38
Pending Applications
7
Abandoned Applications
5

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3981633 [patent_doc_number] => 05887001 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Boundary scan architecture analog extension with direct connections' [patent_app_type] => 1 [patent_app_number] => 8/946952 [patent_app_country] => US [patent_app_date] => 1997-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8759 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/887/05887001.pdf [firstpage_image] =>[orig_patent_app_number] => 946952 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/946952
Boundary scan architecture analog extension with direct connections Oct 7, 1997 Issued
Array ( [id] => 4058192 [patent_doc_number] => 05996099 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method and apparatus for automatically testing electronic components in parallel utilizing different timing signals for each electronic component' [patent_app_type] => 1 [patent_app_number] => 8/930501 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2707 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996099.pdf [firstpage_image] =>[orig_patent_app_number] => 930501 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/930501
Method and apparatus for automatically testing electronic components in parallel utilizing different timing signals for each electronic component Sep 29, 1997 Issued
Array ( [id] => 4115228 [patent_doc_number] => 06049900 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Automatic parallel electronic component testing method and equipment' [patent_app_type] => 1 [patent_app_number] => 8/930492 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2278 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049900.pdf [firstpage_image] =>[orig_patent_app_number] => 930492 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/930492
Automatic parallel electronic component testing method and equipment Sep 29, 1997 Issued
Array ( [id] => 4039798 [patent_doc_number] => 05903577 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Method and apparatus for analyzing digital circuits' [patent_app_type] => 1 [patent_app_number] => 8/940912 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2960 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903577.pdf [firstpage_image] =>[orig_patent_app_number] => 940912 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/940912
Method and apparatus for analyzing digital circuits Sep 29, 1997 Issued
Array ( [id] => 3915986 [patent_doc_number] => 05944846 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Method and apparatus for selectively testing identical pins of a plurality of electronic components' [patent_app_type] => 1 [patent_app_number] => 8/930490 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2627 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/944/05944846.pdf [firstpage_image] =>[orig_patent_app_number] => 930490 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/930490
Method and apparatus for selectively testing identical pins of a plurality of electronic components Sep 29, 1997 Issued
Array ( [id] => 3808916 [patent_doc_number] => 05781562 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Method, system and apparatus for efficiently generating binary numbers for testing storage devices' [patent_app_type] => 1 [patent_app_number] => 8/943911 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3287 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781562.pdf [firstpage_image] =>[orig_patent_app_number] => 943911 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/943911
Method, system and apparatus for efficiently generating binary numbers for testing storage devices Sep 29, 1997 Issued
Array ( [id] => 3968127 [patent_doc_number] => 05983376 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Automated scan insertion flow for control block design' [patent_app_type] => 1 [patent_app_number] => 8/935470 [patent_app_country] => US [patent_app_date] => 1997-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7259 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983376.pdf [firstpage_image] =>[orig_patent_app_number] => 935470 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/935470
Automated scan insertion flow for control block design Sep 23, 1997 Issued
Array ( [id] => 3924290 [patent_doc_number] => 05938780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Method for capturing digital data in an automatic test system' [patent_app_type] => 1 [patent_app_number] => 8/933391 [patent_app_country] => US [patent_app_date] => 1997-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 26 [patent_no_of_words] => 9406 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/938/05938780.pdf [firstpage_image] =>[orig_patent_app_number] => 933391 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/933391
Method for capturing digital data in an automatic test system Sep 18, 1997 Issued
Array ( [id] => 4006213 [patent_doc_number] => 05920574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Method for accelerated test of semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/932894 [patent_app_country] => US [patent_app_date] => 1997-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3207 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920574.pdf [firstpage_image] =>[orig_patent_app_number] => 932894 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/932894
Method for accelerated test of semiconductor devices Sep 17, 1997 Issued
Array ( [id] => 3972079 [patent_doc_number] => 05901155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'System and method for testing the operation of registers in electronic digital systems' [patent_app_type] => 1 [patent_app_number] => 8/925407 [patent_app_country] => US [patent_app_date] => 1997-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6770 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901155.pdf [firstpage_image] =>[orig_patent_app_number] => 925407 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/925407
System and method for testing the operation of registers in electronic digital systems Sep 7, 1997 Issued
Array ( [id] => 4046232 [patent_doc_number] => 05856985 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-05 [patent_title] => 'Test pattern generator' [patent_app_type] => 1 [patent_app_number] => 8/849682 [patent_app_country] => US [patent_app_date] => 1997-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3377 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/856/05856985.pdf [firstpage_image] =>[orig_patent_app_number] => 849682 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/849682
Test pattern generator Sep 7, 1997 Issued
Array ( [id] => 4020500 [patent_doc_number] => 05889787 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Circuit including structural testing means with no dedicated test pad for testing' [patent_app_type] => 1 [patent_app_number] => 8/922611 [patent_app_country] => US [patent_app_date] => 1997-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3255 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889787.pdf [firstpage_image] =>[orig_patent_app_number] => 922611 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/922611
Circuit including structural testing means with no dedicated test pad for testing Sep 2, 1997 Issued
Array ( [id] => 4149170 [patent_doc_number] => 06016562 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Inspection data analyzing apparatus for in-line inspection with enhanced display of inspection results' [patent_app_type] => 1 [patent_app_number] => 8/919166 [patent_app_country] => US [patent_app_date] => 1997-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 9627 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016562.pdf [firstpage_image] =>[orig_patent_app_number] => 919166 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/919166
Inspection data analyzing apparatus for in-line inspection with enhanced display of inspection results Aug 27, 1997 Issued
Array ( [id] => 4178549 [patent_doc_number] => 06108807 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Apparatus and method for hybrid pin control of boundary scan applications' [patent_app_type] => 1 [patent_app_number] => 8/901250 [patent_app_country] => US [patent_app_date] => 1997-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3887 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108807.pdf [firstpage_image] =>[orig_patent_app_number] => 901250 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/901250
Apparatus and method for hybrid pin control of boundary scan applications Jul 27, 1997 Issued
Array ( [id] => 3971391 [patent_doc_number] => 05936976 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Selecting a test data input bus to supply test data to logical blocks within an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/910590 [patent_app_country] => US [patent_app_date] => 1997-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2839 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936976.pdf [firstpage_image] =>[orig_patent_app_number] => 910590 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/910590
Selecting a test data input bus to supply test data to logical blocks within an integrated circuit Jul 24, 1997 Issued
Array ( [id] => 3951930 [patent_doc_number] => 05930270 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Logic built in self-test diagnostic method' [patent_app_type] => 1 [patent_app_number] => 8/898942 [patent_app_country] => US [patent_app_date] => 1997-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4160 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930270.pdf [firstpage_image] =>[orig_patent_app_number] => 898942 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/898942
Logic built in self-test diagnostic method Jul 22, 1997 Issued
Array ( [id] => 3917533 [patent_doc_number] => 05971606 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Module and apparatus for measuring temperature properties of an SRAM IC' [patent_app_type] => 1 [patent_app_number] => 8/910560 [patent_app_country] => US [patent_app_date] => 1997-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1714 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/971/05971606.pdf [firstpage_image] =>[orig_patent_app_number] => 910560 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/910560
Module and apparatus for measuring temperature properties of an SRAM IC Jul 21, 1997 Issued
Array ( [id] => 3971514 [patent_doc_number] => 06000039 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Data reconstruction method and system wherein timing of data reconstruction is controlled in accordance with conditions when a failure occurs' [patent_app_type] => 1 [patent_app_number] => 8/895986 [patent_app_country] => US [patent_app_date] => 1997-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5740 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000039.pdf [firstpage_image] =>[orig_patent_app_number] => 895986 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/895986
Data reconstruction method and system wherein timing of data reconstruction is controlled in accordance with conditions when a failure occurs Jul 16, 1997 Issued
Array ( [id] => 4026373 [patent_doc_number] => 05941993 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Data reconstruction method and system wherein timing of data reconstruction is controlled in accordance with conditions when a failure occurs' [patent_app_type] => 1 [patent_app_number] => 8/895886 [patent_app_country] => US [patent_app_date] => 1997-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5749 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/941/05941993.pdf [firstpage_image] =>[orig_patent_app_number] => 895886 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/895886
Data reconstruction method and system wherein timing of data reconstruction is controlled in accordance with conditions when a failure occurs Jul 16, 1997 Issued
Array ( [id] => 3974386 [patent_doc_number] => 05978948 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Semiconductor circuit system, method for testing semiconductor integrated circuits, and method for generating a test sequence for testing thereof' [patent_app_type] => 1 [patent_app_number] => 8/888920 [patent_app_country] => US [patent_app_date] => 1997-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8281 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978948.pdf [firstpage_image] =>[orig_patent_app_number] => 888920 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/888920
Semiconductor circuit system, method for testing semiconductor integrated circuits, and method for generating a test sequence for testing thereof Jul 6, 1997 Issued
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