Phillip J Groutt

Array ( [id] => 4424993 [patent_doc_number] => 06230290 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Method of self programmed built in self test' [patent_app_type] => 1 [patent_app_number] => 8/887462 [patent_app_country] => US [patent_app_date] => 1997-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3451 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230290.pdf [firstpage_image] =>[orig_patent_app_number] => 887462 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4005955 [patent_doc_number] => 05892778 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Boundary-scan circuit for use with linearized impedance control type output drivers' [patent_app_type] => 1 [patent_app_number] => 8/885012 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 5195 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892778.pdf [firstpage_image] =>[orig_patent_app_number] => 885012 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4257610 [patent_doc_number] => 06081913 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Method for ensuring mutual exclusivity of selected signals during application of test patterns' [patent_app_type] => 1 [patent_app_number] => 8/868161 [patent_app_country] => US [patent_app_date] => 1997-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 5681 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081913.pdf [firstpage_image] =>[orig_patent_app_number] => 868161 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4161288 [patent_doc_number] => 06061816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Timing generator for testing semiconductor storage devices' [patent_app_type] => 1 [patent_app_number] => 8/864910 [patent_app_country] => US [patent_app_date] => 1997-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 5640 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061816.pdf [firstpage_image] =>[orig_patent_app_number] => 864910 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4100600 [patent_doc_number] => 06055655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Semiconductor integrated circuit device and method of testing the same' [patent_app_type] => 1 [patent_app_number] => 8/865371 [patent_app_country] => US [patent_app_date] => 1997-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 88 [patent_no_of_words] => 28208 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055655.pdf [firstpage_image] =>[orig_patent_app_number] => 865371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4039846 [patent_doc_number] => 05903580 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Fault simulator of creating a signal pattern for use in a fault inspection of a semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/861731 [patent_app_country] => US [patent_app_date] => 1997-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 5721 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903580.pdf [firstpage_image] =>[orig_patent_app_number] => 861731 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4055164 [patent_doc_number] => 05909448 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Memory testing apparatus using a failure cell array' [patent_app_type] => 1 [patent_app_number] => 8/836764 [patent_app_country] => US [patent_app_date] => 1997-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8274 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909448.pdf [firstpage_image] =>[orig_patent_app_number] => 836764 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4216131 [patent_doc_number] => 06014764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Providing test vectors with pattern chaining definition' [patent_app_type] => 1 [patent_app_number] => 8/858992 [patent_app_country] => US [patent_app_date] => 1997-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7281 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014764.pdf [firstpage_image] =>[orig_patent_app_number] => 858992 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4025714 [patent_doc_number] => 06006346 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Method and equipment for automatically testing electronic components' [patent_app_type] => 1 [patent_app_number] => 8/849290 [patent_app_country] => US [patent_app_date] => 1997-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4861 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/006/06006346.pdf [firstpage_image] =>[orig_patent_app_number] => 849290 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4127346 [patent_doc_number] => 06058495 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Multi-bit test circuit in semiconductor memory device and method thereof' [patent_app_type] => 1 [patent_app_number] => 8/854300 [patent_app_country] => US [patent_app_date] => 1997-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2701 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058495.pdf [firstpage_image] =>[orig_patent_app_number] => 854300 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3917988 [patent_doc_number] => 05913928 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Data compression test mode independent of redundancy' [patent_app_type] => 1 [patent_app_number] => 8/853263 [patent_app_country] => US [patent_app_date] => 1997-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4262 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/913/05913928.pdf [firstpage_image] =>[orig_patent_app_number] => 853263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4195714 [patent_doc_number] => 06085342 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Electronic system having a chip integrated power-on reset circuit with glitch sensor' [patent_app_type] => 1 [patent_app_number] => 8/851875 [patent_app_country] => US [patent_app_date] => 1997-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4441 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085342.pdf [firstpage_image] =>[orig_patent_app_number] => 851875 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3906435 [patent_doc_number] => 05835506 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Single pass doublet mode integrated circuit tester' [patent_app_type] => 1 [patent_app_number] => 8/845942 [patent_app_country] => US [patent_app_date] => 1997-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 9184 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835506.pdf [firstpage_image] =>[orig_patent_app_number] => 845942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4022974 [patent_doc_number] => 05987635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Semiconductor integrated circuit device capable of simultaneously performing self-test on memory circuits and logic circuits' [patent_app_type] => 1 [patent_app_number] => 8/847992 [patent_app_country] => US [patent_app_date] => 1997-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9032 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987635.pdf [firstpage_image] =>[orig_patent_app_number] => 847992 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3906412 [patent_doc_number] => 05835505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Semiconductor integrated circuit and system incorporating the same' [patent_app_type] => 1 [patent_app_number] => 8/843581 [patent_app_country] => US [patent_app_date] => 1997-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 6727 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835505.pdf [firstpage_image] =>[orig_patent_app_number] => 843581 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4038057 [patent_doc_number] => 05883904 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Method for recoverability via redundant cache arrays' [patent_app_type] => 1 [patent_app_number] => 8/834491 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6144 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/883/05883904.pdf [firstpage_image] =>[orig_patent_app_number] => 834491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3775990 [patent_doc_number] => 05844917 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Method for testing adapter card ASIC using reconfigurable logic' [patent_app_type] => 1 [patent_app_number] => 8/831541 [patent_app_country] => US [patent_app_date] => 1997-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 4023 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844917.pdf [firstpage_image] =>[orig_patent_app_number] => 831541 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3803774 [patent_doc_number] => 05841790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Apparatus for testing an adapter card ASIC with reconfigurable logic' [patent_app_type] => 1 [patent_app_number] => 8/831542 [patent_app_country] => US [patent_app_date] => 1997-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 4029 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841790.pdf [firstpage_image] =>[orig_patent_app_number] => 831542 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3889855 [patent_doc_number] => 05764657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Method and apparatus for generating an optimal test pattern for sequence detection' [patent_app_type] => 1 [patent_app_number] => 8/826882 [patent_app_country] => US [patent_app_date] => 1997-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6665 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764657.pdf [firstpage_image] =>[orig_patent_app_number] => 826882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3775934 [patent_doc_number] => 05844913 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Current mode interface circuitry for an IC test device' [patent_app_type] => 1 [patent_app_number] => 8/833412 [patent_app_country] => US [patent_app_date] => 1997-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4972 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844913.pdf [firstpage_image] =>[orig_patent_app_number] => 833412 [rel_patent_id] =>[rel_patent_doc_number] =>)