Search

Phillip J Groutt

Examiner (ID: 11154)

Most Active Art Unit
2761
Art Unit(s)
2411, 2761
Total Applications
50
Issued Applications
38
Pending Applications
7
Abandoned Applications
5

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3775962 [patent_doc_number] => 05844915 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Method for testing word line leakage in a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/716080 [patent_app_country] => US [patent_app_date] => 1996-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2343 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844915.pdf [firstpage_image] =>[orig_patent_app_number] => 716080 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/716080
Method for testing word line leakage in a semiconductor memory device Sep 18, 1996 Issued
Array ( [id] => 3894105 [patent_doc_number] => 05748646 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Design-for-testability method for path delay faults and test pattern generation method for path delay faults' [patent_app_type] => 1 [patent_app_number] => 8/697510 [patent_app_country] => US [patent_app_date] => 1996-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5988 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748646.pdf [firstpage_image] =>[orig_patent_app_number] => 697510 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/697510
Design-for-testability method for path delay faults and test pattern generation method for path delay faults Aug 25, 1996 Issued
Array ( [id] => 3971376 [patent_doc_number] => 05936975 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Semiconductor memory device with switching circuit for controlling internal addresses in parallel test' [patent_app_type] => 1 [patent_app_number] => 8/701231 [patent_app_country] => US [patent_app_date] => 1996-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 31 [patent_no_of_words] => 3843 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936975.pdf [firstpage_image] =>[orig_patent_app_number] => 701231 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/701231
Semiconductor memory device with switching circuit for controlling internal addresses in parallel test Aug 20, 1996 Issued
Array ( [id] => 3971640 [patent_doc_number] => 06000048 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Combined logic and memory circuit with built-in memory test' [patent_app_type] => 1 [patent_app_number] => 8/696551 [patent_app_country] => US [patent_app_date] => 1996-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5178 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000048.pdf [firstpage_image] =>[orig_patent_app_number] => 696551 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/696551
Combined logic and memory circuit with built-in memory test Aug 13, 1996 Issued
Array ( [id] => 3999886 [patent_doc_number] => 05960009 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Built in shelf test method and apparatus for booth multipliers' [patent_app_type] => 1 [patent_app_number] => 8/694881 [patent_app_country] => US [patent_app_date] => 1996-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 10257 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960009.pdf [firstpage_image] =>[orig_patent_app_number] => 694881 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/694881
Built in shelf test method and apparatus for booth multipliers Aug 8, 1996 Issued
Array ( [id] => 4078762 [patent_doc_number] => 05867505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Method and apparatus for testing an integrated circuit including the step/means for storing an associated test identifier in association with integrated circuit identifier for each test to be performed on the integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/693750 [patent_app_country] => US [patent_app_date] => 1996-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2795 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867505.pdf [firstpage_image] =>[orig_patent_app_number] => 693750 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/693750
Method and apparatus for testing an integrated circuit including the step/means for storing an associated test identifier in association with integrated circuit identifier for each test to be performed on the integrated circuit Aug 6, 1996 Issued
Array ( [id] => 1599955 [patent_doc_number] => 06385160 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Pickup adjusting apparatus of a disk player' [patent_app_type] => B1 [patent_app_number] => 08/686526 [patent_app_country] => US [patent_app_date] => 1996-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1126 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385160.pdf [firstpage_image] =>[orig_patent_app_number] => 08686526 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/686526
Pickup adjusting apparatus of a disk player Jul 25, 1996 Issued
Array ( [id] => 3951108 [patent_doc_number] => 05940588 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Parallel testing of CPU cache and instruction units' [patent_app_type] => 1 [patent_app_number] => 8/685041 [patent_app_country] => US [patent_app_date] => 1996-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3547 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940588.pdf [firstpage_image] =>[orig_patent_app_number] => 685041 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/685041
Parallel testing of CPU cache and instruction units Jul 22, 1996 Issued
Array ( [id] => 3874625 [patent_doc_number] => 05796751 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Technique for sorting high frequency integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/684751 [patent_app_country] => US [patent_app_date] => 1996-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2866 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796751.pdf [firstpage_image] =>[orig_patent_app_number] => 684751 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/684751
Technique for sorting high frequency integrated circuits Jul 21, 1996 Issued
Array ( [id] => 4006198 [patent_doc_number] => 05920573 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Method and apparatus for reducing area and pin count required in design for test of wide data path memories' [patent_app_type] => 1 [patent_app_number] => 8/681190 [patent_app_country] => US [patent_app_date] => 1996-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 11100 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920573.pdf [firstpage_image] =>[orig_patent_app_number] => 681190 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/681190
Method and apparatus for reducing area and pin count required in design for test of wide data path memories Jul 21, 1996 Issued
Array ( [id] => 3803710 [patent_doc_number] => 05841785 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Memory testing apparatus for testing a memory having a plurality of memory cell arrays arranged therein' [patent_app_type] => 1 [patent_app_number] => 8/679761 [patent_app_country] => US [patent_app_date] => 1996-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5162 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841785.pdf [firstpage_image] =>[orig_patent_app_number] => 679761 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/679761
Memory testing apparatus for testing a memory having a plurality of memory cell arrays arranged therein Jul 9, 1996 Issued
Array ( [id] => 3844831 [patent_doc_number] => 05740182 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Method and apparatus for testing a circuit with reduced test pattern constraints' [patent_app_type] => 1 [patent_app_number] => 8/672990 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4858 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740182.pdf [firstpage_image] =>[orig_patent_app_number] => 672990 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/672990
Method and apparatus for testing a circuit with reduced test pattern constraints Jun 30, 1996 Issued
Array ( [id] => 4062234 [patent_doc_number] => 05870409 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Method and apparatus for testing a relatively slow speed component of an intergrated circuit having mixed slow speed and high speed components' [patent_app_type] => 1 [patent_app_number] => 8/671011 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 8652 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870409.pdf [firstpage_image] =>[orig_patent_app_number] => 671011 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/671011
Method and apparatus for testing a relatively slow speed component of an intergrated circuit having mixed slow speed and high speed components Jun 27, 1996 Issued
Array ( [id] => 3704452 [patent_doc_number] => 05661731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Method for shrinking a clock cycle when testing high speed microprocessor designs' [patent_app_type] => 1 [patent_app_number] => 8/672101 [patent_app_country] => US [patent_app_date] => 1996-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2358 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661731.pdf [firstpage_image] =>[orig_patent_app_number] => 672101 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/672101
Method for shrinking a clock cycle when testing high speed microprocessor designs Jun 26, 1996 Issued
Array ( [id] => 4066252 [patent_doc_number] => 05970074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Method and apparatus for measuring threshold characteristic of semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/670492 [patent_app_country] => US [patent_app_date] => 1996-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4912 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970074.pdf [firstpage_image] =>[orig_patent_app_number] => 670492 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/670492
Method and apparatus for measuring threshold characteristic of semiconductor integrated circuit Jun 26, 1996 Issued
08/664431 INSPECTION DATA ANALYZING APPARATUS FOR IN-LINE INSPECTION Jun 17, 1996 Abandoned
Array ( [id] => 3718060 [patent_doc_number] => 05655070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Power fault monitoring circuit with microprocessor reset' [patent_app_type] => 1 [patent_app_number] => 8/664400 [patent_app_country] => US [patent_app_date] => 1996-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3384 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/655/05655070.pdf [firstpage_image] =>[orig_patent_app_number] => 664400 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/664400
Power fault monitoring circuit with microprocessor reset Jun 16, 1996 Issued
Array ( [id] => 3672314 [patent_doc_number] => 05649094 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Self-service diagnostic unit for plural functional devices' [patent_app_type] => 1 [patent_app_number] => 8/662961 [patent_app_country] => US [patent_app_date] => 1996-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 7155 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649094.pdf [firstpage_image] =>[orig_patent_app_number] => 662961 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/662961
Self-service diagnostic unit for plural functional devices Jun 12, 1996 Issued
Array ( [id] => 3897632 [patent_doc_number] => 05748875 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Digital logic simulation/emulation system' [patent_app_type] => 1 [patent_app_number] => 8/661991 [patent_app_country] => US [patent_app_date] => 1996-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 20307 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748875.pdf [firstpage_image] =>[orig_patent_app_number] => 661991 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/661991
Digital logic simulation/emulation system Jun 11, 1996 Issued
08/660932 METHOD AND APPARATUS FOR GENERATING AN OPTIMAL TEST PATTERN FOR SEQUENCE DETECTION Jun 9, 1996 Abandoned
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