Phillip J Groutt

Array ( [id] => 3799668 [patent_doc_number] => 05737342 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Method for in-chip testing of digital circuits of a synchronously sampled data detection channel' [patent_app_type] => 1 [patent_app_number] => 8/656021 [patent_app_country] => US [patent_app_date] => 1996-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 6778 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737342.pdf [firstpage_image] =>[orig_patent_app_number] => 656021 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3894092 [patent_doc_number] => 05748645 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Clock scan design from sizzle global clock and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/654981 [patent_app_country] => US [patent_app_date] => 1996-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5332 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748645.pdf [firstpage_image] =>[orig_patent_app_number] => 654981 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4062206 [patent_doc_number] => 05870407 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Method of screening memory cells at room temperature that would be rejected during hot temperature programming tests' [patent_app_type] => 1 [patent_app_number] => 8/653211 [patent_app_country] => US [patent_app_date] => 1996-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4084 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870407.pdf [firstpage_image] =>[orig_patent_app_number] => 653211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3890756 [patent_doc_number] => 05825785 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Serial input shift register built-in self test circuit for embedded circuits' [patent_app_type] => 1 [patent_app_number] => 8/653572 [patent_app_country] => US [patent_app_date] => 1996-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4695 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825785.pdf [firstpage_image] =>[orig_patent_app_number] => 653572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4039828 [patent_doc_number] => 05903579 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Scan path forming circuit' [patent_app_type] => 1 [patent_app_number] => 8/653471 [patent_app_country] => US [patent_app_date] => 1996-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 33 [patent_no_of_words] => 30092 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 526 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903579.pdf [firstpage_image] =>[orig_patent_app_number] => 653471 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3854628 [patent_doc_number] => 05848074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Method and device for testing content addressable memory circuit and content addressable memory circuit with redundancy function' [patent_app_type] => 1 [patent_app_number] => 8/649281 [patent_app_country] => US [patent_app_date] => 1996-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 79 [patent_figures_cnt] => 166 [patent_no_of_words] => 36748 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/848/05848074.pdf [firstpage_image] =>[orig_patent_app_number] => 649281 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3902055 [patent_doc_number] => 05724505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'Apparatus and method for real-time program monitoring via a serial interface' [patent_app_type] => 1 [patent_app_number] => 8/647852 [patent_app_country] => US [patent_app_date] => 1996-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5982 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/724/05724505.pdf [firstpage_image] =>[orig_patent_app_number] => 647852 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3803760 [patent_doc_number] => 05841789 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Apparatus for testing signal timing and programming delay' [patent_app_type] => 1 [patent_app_number] => 8/647222 [patent_app_country] => US [patent_app_date] => 1996-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5463 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841789.pdf [firstpage_image] =>[orig_patent_app_number] => 647222 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3832227 [patent_doc_number] => 05790562 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Circuit with built-in test and method thereof' [patent_app_type] => 1 [patent_app_number] => 8/643401 [patent_app_country] => US [patent_app_date] => 1996-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3936 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/790/05790562.pdf [firstpage_image] =>[orig_patent_app_number] => 643401 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3707431 [patent_doc_number] => 05677917 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Integrated circuit memory using fusible links in a scan chain' [patent_app_type] => 1 [patent_app_number] => 8/641151 [patent_app_country] => US [patent_app_date] => 1996-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4992 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677917.pdf [firstpage_image] =>[orig_patent_app_number] => 641151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3519814 [patent_doc_number] => 05588007 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-24 [patent_title] => 'Method for detecting transient write errors in a disk drive' [patent_app_type] => 1 [patent_app_number] => 8/639176 [patent_app_country] => US [patent_app_date] => 1996-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2874 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/588/05588007.pdf [firstpage_image] =>[orig_patent_app_number] => 639176 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3875346 [patent_doc_number] => 05793777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'System and method for testing internal nodes of an integrated circuit at any predetermined machine cycle' [patent_app_type] => 1 [patent_app_number] => 8/635352 [patent_app_country] => US [patent_app_date] => 1996-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4070 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793777.pdf [firstpage_image] =>[orig_patent_app_number] => 635352 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3757746 [patent_doc_number] => 05717704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Test system including a local trigger signal generator for each of a plurality of test instruments' [patent_app_type] => 1 [patent_app_number] => 8/633172 [patent_app_country] => US [patent_app_date] => 1996-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 10628 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717704.pdf [firstpage_image] =>[orig_patent_app_number] => 633172 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3812607 [patent_doc_number] => 05828825 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Method and apparatus for pseudo-direct access to embedded memories of a micro-controller integrated circuit via the IEEE test access port' [patent_app_type] => 1 [patent_app_number] => 8/633930 [patent_app_country] => US [patent_app_date] => 1996-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6378 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828825.pdf [firstpage_image] =>[orig_patent_app_number] => 633930 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3823069 [patent_doc_number] => 05710778 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-20 [patent_title] => 'High voltage reference and measurement circuit for verifying a programmable cell' [patent_app_type] => 1 [patent_app_number] => 8/625332 [patent_app_country] => US [patent_app_date] => 1996-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2130 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/710/05710778.pdf [firstpage_image] =>[orig_patent_app_number] => 625332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3868319 [patent_doc_number] => 05768288 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Method and apparatus for programming a programmable logic device having verify logic for comparing verify data read from a memory location with program data' [patent_app_type] => 1 [patent_app_number] => 8/625361 [patent_app_country] => US [patent_app_date] => 1996-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 17949 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768288.pdf [firstpage_image] =>[orig_patent_app_number] => 625361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3846682 [patent_doc_number] => 05815510 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Serial programming of instruction codes in different numbers of clock cycles' [patent_app_type] => 1 [patent_app_number] => 8/624193 [patent_app_country] => US [patent_app_date] => 1996-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 17794 [patent_no_of_claims] => 87 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815510.pdf [firstpage_image] =>[orig_patent_app_number] => 624193 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3889797 [patent_doc_number] => 05764653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Method and apparatus for detecting abnormal operation in a storage circuit by monitoring an associated reference circuit' [patent_app_type] => 1 [patent_app_number] => 8/618921 [patent_app_country] => US [patent_app_date] => 1996-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3183 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764653.pdf [firstpage_image] =>[orig_patent_app_number] => 618921 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3969364 [patent_doc_number] => 05948114 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Integrated circuit binary data output interface for multiplexed output of internal binary information elements from input/output pads' [patent_app_type] => 1 [patent_app_number] => 8/618920 [patent_app_country] => US [patent_app_date] => 1996-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3537 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/948/05948114.pdf [firstpage_image] =>[orig_patent_app_number] => 618920 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3784933 [patent_doc_number] => 05774474 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Pipelined scan enable for fast scan testing' [patent_app_type] => 1 [patent_app_number] => 8/616112 [patent_app_country] => US [patent_app_date] => 1996-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6378 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774474.pdf [firstpage_image] =>[orig_patent_app_number] => 616112 [rel_patent_id] =>[rel_patent_doc_number] =>)