Application number | Title of the application | Filing Date | Status |
---|
Array
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[patent_kind] => NA
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Array
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[patent_kind] => NA
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Array
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[patent_doc_number] => 05844921
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[patent_kind] => NA
[patent_issue_date] => 1998-12-01
[patent_title] => 'Method and apparatus for testing a hybrid circuit having macro and non-macro circuitry'
[patent_app_type] => 1
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[patent_app_country] => US
[patent_app_date] => 1996-02-28
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Array
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-07
[patent_title] => 'System for transmitting desired digital video or audio signals'
[patent_app_type] => 1
[patent_app_number] => 8/607648
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[patent_app_date] => 1996-02-27
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[patent_kind] => NA
[patent_issue_date] => 1997-10-28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/603881 | Apparatus and method for high speed shifting of test data through an integrated circuit | Feb 21, 1996 | Issued |
Array
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[id] => 3741748
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[patent_kind] => NA
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[patent_app_type] => 1
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Array
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[id] => 3765502
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[patent_kind] => NA
[patent_issue_date] => 1998-02-24
[patent_title] => 'Flip-flop controller for selectively disabling clock signal'
[patent_app_type] => 1
[patent_app_number] => 8/590302
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[patent_app_date] => 1996-01-23
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[firstpage_image] =>[orig_patent_app_number] => 590302
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/590302 | Flip-flop controller for selectively disabling clock signal | Jan 22, 1996 | Issued |
Array
(
[id] => 4005927
[patent_doc_number] => 05892776
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-06
[patent_title] => 'Semiconductor memory and test method incorporating selectable clock signal modes'
[patent_app_type] => 1
[patent_app_number] => 8/583938
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/583938 | Semiconductor memory and test method incorporating selectable clock signal modes | Jan 10, 1996 | Issued |
Array
(
[id] => 3630339
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-24
[patent_title] => 'Method and apparatus for testing of electronic assemblies'
[patent_app_type] => 1
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[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 576530
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/576530 | Method and apparatus for testing of electronic assemblies | Dec 20, 1995 | Issued |
Array
(
[id] => 4057308
[patent_doc_number] => 05913022
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-15
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[patent_app_type] => 1
[patent_app_number] => 8/573071
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/573071 | Loading hardware pattern memory in automatic test equipment for testing circuits | Dec 14, 1995 | Issued |
08/572252 | BOUNDARY SCAN ARCHITECTURE EXTENDED TO PROVIDED MIXED SIGNAL OPERATION USING DIRECT CONNECTIONS | Dec 12, 1995 | Abandoned |
Array
(
[id] => 3757708
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[patent_kind] => NA
[patent_issue_date] => 1998-02-10
[patent_title] => 'Method for creating a high speed scan-interconnected set of flip-flop elements in an integrated circuit to enable faster scan-based testing'
[patent_app_type] => 1
[patent_app_number] => 8/566812
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[firstpage_image] =>[orig_patent_app_number] => 566812
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/566812 | Method for creating a high speed scan-interconnected set of flip-flop elements in an integrated circuit to enable faster scan-based testing | Dec 3, 1995 | Issued |
Array
(
[id] => 3739282
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[patent_kind] => NA
[patent_issue_date] => 1997-09-23
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Array
(
[id] => 3757637
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[patent_kind] => NA
[patent_issue_date] => 1998-02-10
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[patent_app_type] => 1
[patent_app_number] => 8/566900
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Array
(
[id] => 3595105
[patent_doc_number] => 05581693
[patent_country] => US
[patent_kind] => NA
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Array
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[patent_kind] => NA
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/562337 | Time-triggered communication control unit and communication method | Nov 23, 1995 | Issued |
Array
(
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[patent_kind] => NA
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/552971 | Method and apparatus for a real-time data collection and display system | Nov 2, 1995 | Issued |
Array
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-25
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[patent_app_type] => 1
[patent_app_number] => 8/552141
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/552141 | System and method of programming a multistation testing system | Nov 1, 1995 | Issued |
08/551955 | SYSTEM AND METHOD OF ACCOUNTING FOR DEFECT DETECTION IN A TESTING SYSTEM | Nov 1, 1995 | Abandoned |