Search

Phillip J Groutt

Examiner (ID: 11154)

Most Active Art Unit
2761
Art Unit(s)
2411, 2761
Total Applications
50
Issued Applications
38
Pending Applications
7
Abandoned Applications
5

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3692181 [patent_doc_number] => 05633882 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Error detection and correction circuit' [patent_app_type] => 1 [patent_app_number] => 8/615033 [patent_app_country] => US [patent_app_date] => 1996-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1679 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/633/05633882.pdf [firstpage_image] =>[orig_patent_app_number] => 615033 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/615033
Error detection and correction circuit Mar 10, 1996 Issued
Array ( [id] => 3805327 [patent_doc_number] => 05726994 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Address multiplex semiconductor memory device for enabling testing of the entire circuit or for only partial components thereof' [patent_app_type] => 1 [patent_app_number] => 8/608616 [patent_app_country] => US [patent_app_date] => 1996-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7661 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 382 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/726/05726994.pdf [firstpage_image] =>[orig_patent_app_number] => 608616 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/608616
Address multiplex semiconductor memory device for enabling testing of the entire circuit or for only partial components thereof Feb 28, 1996 Issued
Array ( [id] => 3776049 [patent_doc_number] => 05844921 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Method and apparatus for testing a hybrid circuit having macro and non-macro circuitry' [patent_app_type] => 1 [patent_app_number] => 8/608591 [patent_app_country] => US [patent_app_date] => 1996-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5373 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844921.pdf [firstpage_image] =>[orig_patent_app_number] => 608591 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/608591
Method and apparatus for testing a hybrid circuit having macro and non-macro circuitry Feb 27, 1996 Issued
Array ( [id] => 3715967 [patent_doc_number] => 05675734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'System for transmitting desired digital video or audio signals' [patent_app_type] => 1 [patent_app_number] => 8/607648 [patent_app_country] => US [patent_app_date] => 1996-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4361 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675734.pdf [firstpage_image] =>[orig_patent_app_number] => 607648 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/607648
System for transmitting desired digital video or audio signals Feb 26, 1996 Issued
Array ( [id] => 3732640 [patent_doc_number] => 05682391 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Apparatus and method for high speed shifting of test data through an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/603881 [patent_app_country] => US [patent_app_date] => 1996-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3124 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682391.pdf [firstpage_image] =>[orig_patent_app_number] => 603881 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/603881
Apparatus and method for high speed shifting of test data through an integrated circuit Feb 21, 1996 Issued
Array ( [id] => 3741748 [patent_doc_number] => 05666368 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'System and method for testing the operation of registers in digital electronic systems' [patent_app_type] => 1 [patent_app_number] => 8/593582 [patent_app_country] => US [patent_app_date] => 1996-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6769 [patent_no_of_claims] => 90 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/666/05666368.pdf [firstpage_image] =>[orig_patent_app_number] => 593582 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/593582
System and method for testing the operation of registers in digital electronic systems Jan 29, 1996 Issued
Array ( [id] => 3765502 [patent_doc_number] => 05721740 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Flip-flop controller for selectively disabling clock signal' [patent_app_type] => 1 [patent_app_number] => 8/590302 [patent_app_country] => US [patent_app_date] => 1996-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 2730 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 348 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721740.pdf [firstpage_image] =>[orig_patent_app_number] => 590302 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/590302
Flip-flop controller for selectively disabling clock signal Jan 22, 1996 Issued
Array ( [id] => 4005927 [patent_doc_number] => 05892776 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Semiconductor memory and test method incorporating selectable clock signal modes' [patent_app_type] => 1 [patent_app_number] => 8/583938 [patent_app_country] => US [patent_app_date] => 1996-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 7329 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892776.pdf [firstpage_image] =>[orig_patent_app_number] => 583938 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/583938
Semiconductor memory and test method incorporating selectable clock signal modes Jan 10, 1996 Issued
Array ( [id] => 3630339 [patent_doc_number] => 05642363 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-24 [patent_title] => 'Method and apparatus for testing of electronic assemblies' [patent_app_type] => 1 [patent_app_number] => 8/576530 [patent_app_country] => US [patent_app_date] => 1995-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2330 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/642/05642363.pdf [firstpage_image] =>[orig_patent_app_number] => 576530 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/576530
Method and apparatus for testing of electronic assemblies Dec 20, 1995 Issued
Array ( [id] => 4057308 [patent_doc_number] => 05913022 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Loading hardware pattern memory in automatic test equipment for testing circuits' [patent_app_type] => 1 [patent_app_number] => 8/573071 [patent_app_country] => US [patent_app_date] => 1995-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5070 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/913/05913022.pdf [firstpage_image] =>[orig_patent_app_number] => 573071 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/573071
Loading hardware pattern memory in automatic test equipment for testing circuits Dec 14, 1995 Issued
08/572252 BOUNDARY SCAN ARCHITECTURE EXTENDED TO PROVIDED MIXED SIGNAL OPERATION USING DIRECT CONNECTIONS Dec 12, 1995 Abandoned
Array ( [id] => 3757708 [patent_doc_number] => 05717700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Method for creating a high speed scan-interconnected set of flip-flop elements in an integrated circuit to enable faster scan-based testing' [patent_app_type] => 1 [patent_app_number] => 8/566812 [patent_app_country] => US [patent_app_date] => 1995-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 11041 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717700.pdf [firstpage_image] =>[orig_patent_app_number] => 566812 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/566812
Method for creating a high speed scan-interconnected set of flip-flop elements in an integrated circuit to enable faster scan-based testing Dec 3, 1995 Issued
Array ( [id] => 3739282 [patent_doc_number] => 05671235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Scan chain for shifting the state of a processor into memory at a specified point during system operation for testing purposes' [patent_app_type] => 1 [patent_app_number] => 8/567082 [patent_app_country] => US [patent_app_date] => 1995-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2919 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/671/05671235.pdf [firstpage_image] =>[orig_patent_app_number] => 567082 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/567082
Scan chain for shifting the state of a processor into memory at a specified point during system operation for testing purposes Dec 3, 1995 Issued
Array ( [id] => 3757637 [patent_doc_number] => 05717695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Output pin for selectively outputting one of a plurality of signals internal to a semiconductor chip according to a programmable register for diagnostics' [patent_app_type] => 1 [patent_app_number] => 8/566900 [patent_app_country] => US [patent_app_date] => 1995-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2254 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717695.pdf [firstpage_image] =>[orig_patent_app_number] => 566900 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/566900
Output pin for selectively outputting one of a plurality of signals internal to a semiconductor chip according to a programmable register for diagnostics Dec 3, 1995 Issued
Array ( [id] => 3595105 [patent_doc_number] => 05581693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Method and apparatus for inhibiting computer interface clocks during diagnostic testing' [patent_app_type] => 1 [patent_app_number] => 8/566278 [patent_app_country] => US [patent_app_date] => 1995-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2125 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581693.pdf [firstpage_image] =>[orig_patent_app_number] => 566278 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/566278
Method and apparatus for inhibiting computer interface clocks during diagnostic testing Nov 30, 1995 Issued
Array ( [id] => 3744790 [patent_doc_number] => 05694542 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Time-triggered communication control unit and communication method' [patent_app_type] => 1 [patent_app_number] => 8/562337 [patent_app_country] => US [patent_app_date] => 1995-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5934 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694542.pdf [firstpage_image] =>[orig_patent_app_number] => 562337 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/562337
Time-triggered communication control unit and communication method Nov 23, 1995 Issued
Array ( [id] => 3757866 [patent_doc_number] => 05802071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Micro-controller with a built-in test circuit and method for testing the same' [patent_app_type] => 1 [patent_app_number] => 8/560311 [patent_app_country] => US [patent_app_date] => 1995-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1791 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802071.pdf [firstpage_image] =>[orig_patent_app_number] => 560311 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/560311
Micro-controller with a built-in test circuit and method for testing the same Nov 16, 1995 Issued
Array ( [id] => 3897725 [patent_doc_number] => 05748881 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Method and apparatus for a real-time data collection and display system' [patent_app_type] => 1 [patent_app_number] => 8/552971 [patent_app_country] => US [patent_app_date] => 1995-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5646 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748881.pdf [firstpage_image] =>[orig_patent_app_number] => 552971 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/552971
Method and apparatus for a real-time data collection and display system Nov 2, 1995 Issued
Array ( [id] => 3631446 [patent_doc_number] => 05615219 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'System and method of programming a multistation testing system' [patent_app_type] => 1 [patent_app_number] => 8/552141 [patent_app_country] => US [patent_app_date] => 1995-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 8568 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/615/05615219.pdf [firstpage_image] =>[orig_patent_app_number] => 552141 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/552141
System and method of programming a multistation testing system Nov 1, 1995 Issued
08/551955 SYSTEM AND METHOD OF ACCOUNTING FOR DEFECT DETECTION IN A TESTING SYSTEM Nov 1, 1995 Abandoned
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