Search

Phillip J Groutt

Examiner (ID: 11154)

Most Active Art Unit
2761
Art Unit(s)
2411, 2761
Total Applications
50
Issued Applications
38
Pending Applications
7
Abandoned Applications
5

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4224583 [patent_doc_number] => 06079036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Call message with traveling log for testing intelligent telecommunications network' [patent_app_type] => 1 [patent_app_number] => 8/545183 [patent_app_country] => US [patent_app_date] => 1995-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 7482 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/079/06079036.pdf [firstpage_image] =>[orig_patent_app_number] => 545183 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/545183
Call message with traveling log for testing intelligent telecommunications network Oct 18, 1995 Issued
Array ( [id] => 3698668 [patent_doc_number] => 05663967 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Defect isolation using scan-path testing and electron beam probing in multi-level high density asics' [patent_app_type] => 1 [patent_app_number] => 8/545462 [patent_app_country] => US [patent_app_date] => 1995-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5057 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/663/05663967.pdf [firstpage_image] =>[orig_patent_app_number] => 545462 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/545462
Defect isolation using scan-path testing and electron beam probing in multi-level high density asics Oct 18, 1995 Issued
Array ( [id] => 3728703 [patent_doc_number] => 05617427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-01 [patent_title] => 'Method for generating test sequences for detecting faults in target scan logical blocks' [patent_app_type] => 1 [patent_app_number] => 8/544162 [patent_app_country] => US [patent_app_date] => 1995-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 6716 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/617/05617427.pdf [firstpage_image] =>[orig_patent_app_number] => 544162 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/544162
Method for generating test sequences for detecting faults in target scan logical blocks Oct 16, 1995 Issued
Array ( [id] => 3667518 [patent_doc_number] => 05659552 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Method and apparatus for verifying test information on a backplane test bus' [patent_app_type] => 1 [patent_app_number] => 8/544351 [patent_app_country] => US [patent_app_date] => 1995-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3715 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659552.pdf [firstpage_image] =>[orig_patent_app_number] => 544351 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/544351
Method and apparatus for verifying test information on a backplane test bus Oct 16, 1995 Issued
Array ( [id] => 3560853 [patent_doc_number] => 05546533 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => 'Dynamic device reconfiguration having restricted main storage access for subsystem employing magnetic units' [patent_app_type] => 1 [patent_app_number] => 8/543771 [patent_app_country] => US [patent_app_date] => 1995-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 11283 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/546/05546533.pdf [firstpage_image] =>[orig_patent_app_number] => 543771 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/543771
Dynamic device reconfiguration having restricted main storage access for subsystem employing magnetic units Oct 15, 1995 Issued
Array ( [id] => 3994443 [patent_doc_number] => 05910958 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Automatic generation of test vectors for sequential circuits' [patent_app_type] => 1 [patent_app_number] => 8/539887 [patent_app_country] => US [patent_app_date] => 1995-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5842 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/910/05910958.pdf [firstpage_image] =>[orig_patent_app_number] => 539887 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/539887
Automatic generation of test vectors for sequential circuits Oct 5, 1995 Issued
Array ( [id] => 3698641 [patent_doc_number] => 05663965 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Apparatus and method for testing a memory array' [patent_app_type] => 1 [patent_app_number] => 8/539932 [patent_app_country] => US [patent_app_date] => 1995-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3023 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/663/05663965.pdf [firstpage_image] =>[orig_patent_app_number] => 539932 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/539932
Apparatus and method for testing a memory array Oct 5, 1995 Issued
Array ( [id] => 3563845 [patent_doc_number] => 05574734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'Test generation of sequential circuits using software transformations' [patent_app_type] => 1 [patent_app_number] => 8/539392 [patent_app_country] => US [patent_app_date] => 1995-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6460 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/574/05574734.pdf [firstpage_image] =>[orig_patent_app_number] => 539392 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/539392
Test generation of sequential circuits using software transformations Oct 4, 1995 Issued
Array ( [id] => 4022906 [patent_doc_number] => 05889938 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Data reconstruction method and system wherein timing of data reconstruction is controlled in accordance with conditions when a failure occurs' [patent_app_type] => 1 [patent_app_number] => 8/534841 [patent_app_country] => US [patent_app_date] => 1995-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5753 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889938.pdf [firstpage_image] =>[orig_patent_app_number] => 534841 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/534841
Data reconstruction method and system wherein timing of data reconstruction is controlled in accordance with conditions when a failure occurs Sep 26, 1995 Issued
Array ( [id] => 3667532 [patent_doc_number] => 05659553 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Comparison circuit for comparing semiconductor device output by strobe signal timing' [patent_app_type] => 1 [patent_app_number] => 8/532421 [patent_app_country] => US [patent_app_date] => 1995-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3323 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659553.pdf [firstpage_image] =>[orig_patent_app_number] => 532421 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/532421
Comparison circuit for comparing semiconductor device output by strobe signal timing Sep 21, 1995 Issued
Array ( [id] => 3847333 [patent_doc_number] => 05740351 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Apparatus and method for debugging/modifying ROM-based software systems employing and extensible interpreter' [patent_app_type] => 1 [patent_app_number] => 8/527463 [patent_app_country] => US [patent_app_date] => 1995-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2608 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740351.pdf [firstpage_image] =>[orig_patent_app_number] => 527463 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/527463
Apparatus and method for debugging/modifying ROM-based software systems employing and extensible interpreter Sep 12, 1995 Issued
Array ( [id] => 3859370 [patent_doc_number] => 05719877 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-17 [patent_title] => 'Scan test' [patent_app_type] => 1 [patent_app_number] => 8/519052 [patent_app_country] => US [patent_app_date] => 1995-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 10257 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/719/05719877.pdf [firstpage_image] =>[orig_patent_app_number] => 519052 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/519052
Scan test Aug 23, 1995 Issued
Array ( [id] => 3859358 [patent_doc_number] => 05719876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-17 [patent_title] => 'Scan latch using half latches' [patent_app_type] => 1 [patent_app_number] => 8/519051 [patent_app_country] => US [patent_app_date] => 1995-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 10081 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/719/05719876.pdf [firstpage_image] =>[orig_patent_app_number] => 519051 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/519051
Scan latch using half latches Aug 23, 1995 Issued
Array ( [id] => 3563830 [patent_doc_number] => 05574733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'Scan-based built-in self test (BIST) with automatic reseeding of pattern generator' [patent_app_type] => 1 [patent_app_number] => 8/506661 [patent_app_country] => US [patent_app_date] => 1995-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4789 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/574/05574733.pdf [firstpage_image] =>[orig_patent_app_number] => 506661 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/506661
Scan-based built-in self test (BIST) with automatic reseeding of pattern generator Jul 24, 1995 Issued
Array ( [id] => 3585366 [patent_doc_number] => 05539878 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-23 [patent_title] => 'Parallel testing of CPU cache and instruction units' [patent_app_type] => 1 [patent_app_number] => 8/491157 [patent_app_country] => US [patent_app_date] => 1995-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3547 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/539/05539878.pdf [firstpage_image] =>[orig_patent_app_number] => 491157 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/491157
Parallel testing of CPU cache and instruction units Jun 15, 1995 Issued
08/488941 METHOD, SYSTEM AND APPARATUS FOR EFFICIENTLY GENERATING BINARY NUMBERS FOR TESTING STORAGE DEVICES Jun 8, 1995 Abandoned
Array ( [id] => 3806320 [patent_doc_number] => 05841961 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Semiconductor memory device including a tag memory' [patent_app_type] => 1 [patent_app_number] => 8/487214 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 8235 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841961.pdf [firstpage_image] =>[orig_patent_app_number] => 487214 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/487214
Semiconductor memory device including a tag memory Jun 6, 1995 Issued
Array ( [id] => 3832254 [patent_doc_number] => 05790564 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/485296 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5163 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/790/05790564.pdf [firstpage_image] =>[orig_patent_app_number] => 485296 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/485296
Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor Jun 6, 1995 Issued
Array ( [id] => 3633578 [patent_doc_number] => 05612963 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'Hybrid pattern self-testing of integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/486100 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4228 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/612/05612963.pdf [firstpage_image] =>[orig_patent_app_number] => 486100 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/486100
Hybrid pattern self-testing of integrated circuits Jun 6, 1995 Issued
Array ( [id] => 3672209 [patent_doc_number] => 05592616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Method for performing efficient memory testing on large memory arrays using test code executed from cache memory' [patent_app_type] => 1 [patent_app_number] => 8/481634 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2959 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/592/05592616.pdf [firstpage_image] =>[orig_patent_app_number] => 481634 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/481634
Method for performing efficient memory testing on large memory arrays using test code executed from cache memory Jun 6, 1995 Issued
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