Application number | Title of the application | Filing Date | Status |
---|
Array
(
[id] => 3561921
[patent_doc_number] => 05548715
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-20
[patent_title] => 'Analysis of untestable faults using discrete node sets'
[patent_app_type] => 1
[patent_app_number] => 8/258166
[patent_app_country] => US
[patent_app_date] => 1994-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 21
[patent_no_of_words] => 6722
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/548/05548715.pdf
[firstpage_image] =>[orig_patent_app_number] => 258166
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/258166 | Analysis of untestable faults using discrete node sets | Jun 9, 1994 | Issued |
Array
(
[id] => 3588661
[patent_doc_number] => 05524208
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-04
[patent_title] => 'Method and apparatus for performing cache snoop testing using DMA cycles in a computer system'
[patent_app_type] => 1
[patent_app_number] => 8/257404
[patent_app_country] => US
[patent_app_date] => 1994-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6651
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/524/05524208.pdf
[firstpage_image] =>[orig_patent_app_number] => 257404
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/257404 | Method and apparatus for performing cache snoop testing using DMA cycles in a computer system | Jun 8, 1994 | Issued |
Array
(
[id] => 3602380
[patent_doc_number] => 05568492
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-22
[patent_title] => 'Circuit and method of JTAG testing multichip modules'
[patent_app_type] => 1
[patent_app_number] => 8/254846
[patent_app_country] => US
[patent_app_date] => 1994-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5407
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/568/05568492.pdf
[firstpage_image] =>[orig_patent_app_number] => 254846
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/254846 | Circuit and method of JTAG testing multichip modules | Jun 5, 1994 | Issued |
Array
(
[id] => 3974309
[patent_doc_number] => 05978945
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-02
[patent_title] => 'Tester arrangement comprising a connection module for testing, by way of the boundary scan test method, a carrier provided with a first number of digital ICS with BST logic and a second number of digital ICS without BST logic'
[patent_app_type] => 1
[patent_app_number] => 8/249427
[patent_app_country] => US
[patent_app_date] => 1994-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 4
[patent_no_of_words] => 2675
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/978/05978945.pdf
[firstpage_image] =>[orig_patent_app_number] => 249427
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/249427 | Tester arrangement comprising a connection module for testing, by way of the boundary scan test method, a carrier provided with a first number of digital ICS with BST logic and a second number of digital ICS without BST logic | May 25, 1994 | Issued |
Array
(
[id] => 3637391
[patent_doc_number] => 05621740
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-15
[patent_title] => 'Output pad circuit for detecting short faults in integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 8/242673
[patent_app_country] => US
[patent_app_date] => 1994-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 45
[patent_no_of_words] => 16555
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/621/05621740.pdf
[firstpage_image] =>[orig_patent_app_number] => 242673
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/242673 | Output pad circuit for detecting short faults in integrated circuits | May 12, 1994 | Issued |
08/239923 | FAILURE DETECTION SYSTEM | May 8, 1994 | Abandoned |
Array
(
[id] => 3438985
[patent_doc_number] => 05463635
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-31
[patent_title] => 'Semiconductor memory device including means for checking the operation of an internal address generator'
[patent_app_type] => 1
[patent_app_number] => 8/234600
[patent_app_country] => US
[patent_app_date] => 1994-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2409
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/463/05463635.pdf
[firstpage_image] =>[orig_patent_app_number] => 234600
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/234600 | Semiconductor memory device including means for checking the operation of an internal address generator | Apr 27, 1994 | Issued |
Array
(
[id] => 3004668
[patent_doc_number] => 05367509
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-22
[patent_title] => 'Method for reproducing information recorded on a magneto-optical recording medium including servo controlling the dimension of the reproduction region of the recording medium by means of a recorded signal'
[patent_app_type] => 1
[patent_app_number] => 8/233555
[patent_app_country] => US
[patent_app_date] => 1994-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 19
[patent_no_of_words] => 7048
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 313
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/367/05367509.pdf
[firstpage_image] =>[orig_patent_app_number] => 233555
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/233555 | Method for reproducing information recorded on a magneto-optical recording medium including servo controlling the dimension of the reproduction region of the recording medium by means of a recorded signal | Apr 25, 1994 | Issued |
Array
(
[id] => 3566899
[patent_doc_number] => 05500940
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-19
[patent_title] => 'Method for evaluating failure in an electronic data storage system and preemptive notification thereof, and system with component failure evaluation'
[patent_app_type] => 1
[patent_app_number] => 8/233024
[patent_app_country] => US
[patent_app_date] => 1994-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 4969
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/500/05500940.pdf
[firstpage_image] =>[orig_patent_app_number] => 233024
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/233024 | Method for evaluating failure in an electronic data storage system and preemptive notification thereof, and system with component failure evaluation | Apr 24, 1994 | Issued |
08/232451 | AUTOMATIC PERFORMING SYSTEM WITH DETECTION AND CORRECTION OF ERRORS IN PERFORMANCE INFORMATION | Apr 21, 1994 | Abandoned |
Array
(
[id] => 3605424
[patent_doc_number] => 05522035
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-28
[patent_title] => 'Buffer memory self-diagnosis method for information signal processing apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/230094
[patent_app_country] => US
[patent_app_date] => 1994-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 3559
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/522/05522035.pdf
[firstpage_image] =>[orig_patent_app_number] => 230094
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/230094 | Buffer memory self-diagnosis method for information signal processing apparatus | Apr 19, 1994 | Issued |
Array
(
[id] => 3600666
[patent_doc_number] => 05550974
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-27
[patent_title] => 'Testable memory array which is immune to multiple wordline assertions during scan testing'
[patent_app_type] => 1
[patent_app_number] => 8/228544
[patent_app_country] => US
[patent_app_date] => 1994-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3926
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/550/05550974.pdf
[firstpage_image] =>[orig_patent_app_number] => 228544
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/228544 | Testable memory array which is immune to multiple wordline assertions during scan testing | Apr 14, 1994 | Issued |
Array
(
[id] => 3638024
[patent_doc_number] => 05608867
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-04
[patent_title] => 'Debugging system using virtual storage means, a normal bus cycle and a debugging bus cycle'
[patent_app_type] => 1
[patent_app_number] => 8/223654
[patent_app_country] => US
[patent_app_date] => 1994-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8395
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 425
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/608/05608867.pdf
[firstpage_image] =>[orig_patent_app_number] => 223654
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/223654 | Debugging system using virtual storage means, a normal bus cycle and a debugging bus cycle | Apr 4, 1994 | Issued |
Array
(
[id] => 4257564
[patent_doc_number] => 06081910
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-27
[patent_title] => 'Circuit for allowing a two-pass fuse blow to memory chips combining an array built-in self-test with redundancy capabilities'
[patent_app_type] => 1
[patent_app_number] => 8/222784
[patent_app_country] => US
[patent_app_date] => 1994-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 6166
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 283
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/081/06081910.pdf
[firstpage_image] =>[orig_patent_app_number] => 222784
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/222784 | Circuit for allowing a two-pass fuse blow to memory chips combining an array built-in self-test with redundancy capabilities | Apr 3, 1994 | Issued |
08/217755 | MAGNETO-OPTICAL RECORDING APPARATUS CAPABLE OF BOTH MAGNETIC MODULATION AND LIGHT MODULATION RECORDING | Mar 24, 1994 | Abandoned |
08/214214 | A SMEICONDUCTOR MEMORY DEVEICE FOR ENABLING TESTING OF THE ENTIRE CIRCUIT OR FOR ONLY PARTIAL COMPONENTS THEREOF | Mar 16, 1994 | Abandoned |
Array
(
[id] => 3527795
[patent_doc_number] => 05506849
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-09
[patent_title] => 'Semiconductor memory device capable of performing an overall test thereon at a shortened time period'
[patent_app_type] => 1
[patent_app_number] => 8/214224
[patent_app_country] => US
[patent_app_date] => 1994-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 3582
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/506/05506849.pdf
[firstpage_image] =>[orig_patent_app_number] => 214224
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/214224 | Semiconductor memory device capable of performing an overall test thereon at a shortened time period | Mar 16, 1994 | Issued |
Array
(
[id] => 3429119
[patent_doc_number] => 05479414
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-26
[patent_title] => 'Look ahead pattern generation and simulation including support for parallel fault simulation in LSSD/VLSI logic circuit testing'
[patent_app_type] => 1
[patent_app_number] => 8/215165
[patent_app_country] => US
[patent_app_date] => 1994-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 4722
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/479/05479414.pdf
[firstpage_image] =>[orig_patent_app_number] => 215165
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/215165 | Look ahead pattern generation and simulation including support for parallel fault simulation in LSSD/VLSI logic circuit testing | Mar 6, 1994 | Issued |
Array
(
[id] => 4057940
[patent_doc_number] => RE036671
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-25
[patent_title] => 'Dual channel readback recovery system'
[patent_app_type] => 2
[patent_app_number] => 8/206042
[patent_app_country] => US
[patent_app_date] => 1994-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 3807
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 30
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/036/RE036671.pdf
[firstpage_image] =>[orig_patent_app_number] => 206042
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/206042 | Dual channel readback recovery system | Mar 3, 1994 | Issued |
Array
(
[id] => 3432716
[patent_doc_number] => 05479651
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-26
[patent_title] => 'Disc drive controller to detect defects in read/write circuits for a disc drive'
[patent_app_type] => 1
[patent_app_number] => 8/204494
[patent_app_country] => US
[patent_app_date] => 1994-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9151
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/479/05479651.pdf
[firstpage_image] =>[orig_patent_app_number] => 204494
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/204494 | Disc drive controller to detect defects in read/write circuits for a disc drive | Mar 1, 1994 | Issued |