Search

Pho M. Luu

Examiner (ID: 10076, Phone: (571)272-1876 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2811, 2824, 2818
Total Applications
2504
Issued Applications
2367
Pending Applications
104
Abandoned Applications
66

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19820671 [patent_doc_number] => 20250078878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 18/952783 [patent_app_country] => US [patent_app_date] => 2024-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18952783 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/952783
MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME Nov 18, 2024 Pending
Array ( [id] => 19803726 [patent_doc_number] => 20250069651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => BISTABLE CIRCUIT AND ELECTRONIC CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/947451 [patent_app_country] => US [patent_app_date] => 2024-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 41220 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18947451 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/947451
BISTABLE CIRCUIT AND ELECTRONIC CIRCUIT Nov 13, 2024 Pending
Array ( [id] => 19790114 [patent_doc_number] => 20250063793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND ASSOCIATED MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/937075 [patent_app_country] => US [patent_app_date] => 2024-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5964 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18937075 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/937075
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND ASSOCIATED MEMORY DEVICE Nov 4, 2024 Pending
Array ( [id] => 20250873 [patent_doc_number] => 20250299742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => DATA STORAGE DEVICE WHICH ERASES BY GROUPING MEMORY BLOCKS AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/935651 [patent_app_country] => US [patent_app_date] => 2024-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 905 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18935651 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/935651
DATA STORAGE DEVICE WHICH ERASES BY GROUPING MEMORY BLOCKS AND METHOD OF OPERATING THE SAME Nov 3, 2024 Pending
Array ( [id] => 19773095 [patent_doc_number] => 20250054521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/928444 [patent_app_country] => US [patent_app_date] => 2024-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18928444 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/928444
SEMICONDUCTOR DEVICE Oct 27, 2024 Pending
Array ( [id] => 19757791 [patent_doc_number] => 20250046356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => MEMORY AND ACCESS METHOD [patent_app_type] => utility [patent_app_number] => 18/921132 [patent_app_country] => US [patent_app_date] => 2024-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18921132 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/921132
MEMORY AND ACCESS METHOD Oct 20, 2024 Pending
Array ( [id] => 20044603 [patent_doc_number] => 20250182825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => CONTENT ADDRESSABLE MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/893127 [patent_app_country] => US [patent_app_date] => 2024-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5887 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18893127 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/893127
CONTENT ADDRESSABLE MEMORY DEVICE AND OPERATING METHOD THEREOF Sep 22, 2024 Pending
Array ( [id] => 20071850 [patent_doc_number] => 20250210072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => BITLINE SENSING AMPLIFIER AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/883399 [patent_app_country] => US [patent_app_date] => 2024-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18883399 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/883399
BITLINE SENSING AMPLIFIER AND MEMORY DEVICE INCLUDING THE SAME Sep 11, 2024 Pending
Array ( [id] => 19986774 [patent_doc_number] => 20250124996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/826151 [patent_app_country] => US [patent_app_date] => 2024-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18826151 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/826151
SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF Sep 4, 2024 Pending
Array ( [id] => 19820731 [patent_doc_number] => 20250078938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/823541 [patent_app_country] => US [patent_app_date] => 2024-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16270 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18823541 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/823541
VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE Sep 2, 2024 Pending
Array ( [id] => 20572051 [patent_doc_number] => 20260065979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-05 [patent_title] => BIT LINE CHARGE SHARING FOR SRAM DYNAMIC POWER SAVINGS [patent_app_type] => utility [patent_app_number] => 18/823460 [patent_app_country] => US [patent_app_date] => 2024-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18823460 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/823460
BIT LINE CHARGE SHARING FOR SRAM DYNAMIC POWER SAVINGS Sep 2, 2024 Pending
Array ( [id] => 19850412 [patent_doc_number] => 20250095763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => TEST APPARATUS AND TEST METHOD [patent_app_type] => utility [patent_app_number] => 18/814460 [patent_app_country] => US [patent_app_date] => 2024-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16484 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18814460 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/814460
TEST APPARATUS AND TEST METHOD Aug 22, 2024 Pending
Array ( [id] => 20071870 [patent_doc_number] => 20250210092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 18/797883 [patent_app_country] => US [patent_app_date] => 2024-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18797883 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/797883
INTEGRATED CIRCUIT DEVICE Aug 7, 2024 Pending
Array ( [id] => 20475980 [patent_doc_number] => 20260018201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-15 [patent_title] => Pulse Signal Generator System for a Magnetoresistive Random Access Memory Array [patent_app_type] => utility [patent_app_number] => 18/789717 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18789717 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/789717
Pulse signal generator system for a magnetoresistive random access memory array Jul 30, 2024 Issued
Array ( [id] => 19773111 [patent_doc_number] => 20250054537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => METHOD AND SYSTEM TO BALANCE GROUND BOUNCE [patent_app_type] => utility [patent_app_number] => 18/788879 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 362 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788879 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/788879
METHOD AND SYSTEM TO BALANCE GROUND BOUNCE Jul 29, 2024 Pending
Array ( [id] => 20010853 [patent_doc_number] => 20250149075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => SEMICONDUCTOR DEVICE AND MEMORY MODULE [patent_app_type] => utility [patent_app_number] => 18/788898 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788898 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/788898
SEMICONDUCTOR DEVICE AND MEMORY MODULE Jul 29, 2024 Pending
Array ( [id] => 20501696 [patent_doc_number] => 20260031158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-29 [patent_title] => SELECTIVE USAGE OF CONCURRENT READ SCANS FOR READ DISTURB SCANNING [patent_app_type] => utility [patent_app_number] => 18/787082 [patent_app_country] => US [patent_app_date] => 2024-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3746 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18787082 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/787082
SELECTIVE USAGE OF CONCURRENT READ SCANS FOR READ DISTURB SCANNING Jul 28, 2024 Pending
Array ( [id] => 20198781 [patent_doc_number] => 20250275491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => Three-Dimensional Structure of Polarity Memory Chalcogenide [patent_app_type] => utility [patent_app_number] => 18/781354 [patent_app_country] => US [patent_app_date] => 2024-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18781354 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/781354
Three-Dimensional Structure of Polarity Memory Chalcogenide Jul 22, 2024 Pending
Array ( [id] => 19559656 [patent_doc_number] => 20240371448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/775119 [patent_app_country] => US [patent_app_date] => 2024-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5504 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18775119 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/775119
SEMICONDUCTOR DEVICE Jul 16, 2024 Pending
Array ( [id] => 19559626 [patent_doc_number] => 20240371418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => CIRCUITS AND METHODS OF MITIGATING HOLD TIME FAILURE OF PIPELINE FOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/772714 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772714 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/772714
Circuits and methods of mitigating hold time failure of pipeline for memory device Jul 14, 2024 Issued
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