Search

Pho M. Luu

Examiner (ID: 10261, Phone: (571)272-1876 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824, 2818, 2811
Total Applications
2470
Issued Applications
2348
Pending Applications
100
Abandoned Applications
66

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19773111 [patent_doc_number] => 20250054537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => METHOD AND SYSTEM TO BALANCE GROUND BOUNCE [patent_app_type] => utility [patent_app_number] => 18/788879 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 362 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788879 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/788879
METHOD AND SYSTEM TO BALANCE GROUND BOUNCE Jul 29, 2024 Pending
Array ( [id] => 19773111 [patent_doc_number] => 20250054537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => METHOD AND SYSTEM TO BALANCE GROUND BOUNCE [patent_app_type] => utility [patent_app_number] => 18/788879 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 362 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788879 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/788879
METHOD AND SYSTEM TO BALANCE GROUND BOUNCE Jul 29, 2024 Pending
Array ( [id] => 19559626 [patent_doc_number] => 20240371418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => CIRCUITS AND METHODS OF MITIGATING HOLD TIME FAILURE OF PIPELINE FOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/772714 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772714 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/772714
Circuits and methods of mitigating hold time failure of pipeline for memory device Jul 14, 2024 Issued
Array ( [id] => 19559626 [patent_doc_number] => 20240371418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => CIRCUITS AND METHODS OF MITIGATING HOLD TIME FAILURE OF PIPELINE FOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/772714 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772714 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/772714
Circuits and methods of mitigating hold time failure of pipeline for memory device Jul 14, 2024 Issued
Array ( [id] => 19546123 [patent_doc_number] => 20240363159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => MEMORY DEVICE, INTEGRATED CIRCUIT DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/769120 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15390 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18769120 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/769120
MEMORY DEVICE, INTEGRATED CIRCUIT DEVICE AND METHOD Jul 9, 2024 Pending
Array ( [id] => 19515433 [patent_doc_number] => 20240347119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => MANAGING PROGRAM VERIFY VOLTAGE OFFSETS FOR CHARGE COUPLING AND LATERAL MIGRATION COMPENSATION IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/753717 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18753717 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/753717
MANAGING PROGRAM VERIFY VOLTAGE OFFSETS FOR CHARGE COUPLING AND LATERAL MIGRATION COMPENSATION IN MEMORY DEVICES Jun 24, 2024 Pending
Array ( [id] => 20214954 [patent_doc_number] => 12411606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => High capacity memory circuit with low effective latency [patent_app_type] => utility [patent_app_number] => 18/750979 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 9805 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18750979 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/750979
High capacity memory circuit with low effective latency Jun 20, 2024 Issued
Array ( [id] => 19694713 [patent_doc_number] => 20250013258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => SYSTEMS AND TECHNIQUES FOR CLOCK DOUBLING [patent_app_type] => utility [patent_app_number] => 18/749057 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749057 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749057
SYSTEMS AND TECHNIQUES FOR CLOCK DOUBLING Jun 19, 2024 Pending
Array ( [id] => 19694713 [patent_doc_number] => 20250013258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => SYSTEMS AND TECHNIQUES FOR CLOCK DOUBLING [patent_app_type] => utility [patent_app_number] => 18/749057 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749057 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749057
SYSTEMS AND TECHNIQUES FOR CLOCK DOUBLING Jun 19, 2024 Pending
Array ( [id] => 19500143 [patent_doc_number] => 20240339161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => NON-VOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/749001 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749001 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749001
NON-VOLATILE MEMORY DEVICE Jun 19, 2024 Pending
Array ( [id] => 19694713 [patent_doc_number] => 20250013258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => SYSTEMS AND TECHNIQUES FOR CLOCK DOUBLING [patent_app_type] => utility [patent_app_number] => 18/749057 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749057 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749057
SYSTEMS AND TECHNIQUES FOR CLOCK DOUBLING Jun 19, 2024 Pending
Array ( [id] => 19500143 [patent_doc_number] => 20240339161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => NON-VOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/749001 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749001 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749001
NON-VOLATILE MEMORY DEVICE Jun 19, 2024 Pending
Array ( [id] => 19486798 [patent_doc_number] => 20240334840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => MAGNETIC TUNNELING JUNCTION DEVICE AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/742115 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742115 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/742115
MAGNETIC TUNNELING JUNCTION DEVICE AND MEMORY DEVICE INCLUDING THE SAME Jun 12, 2024 Pending
Array ( [id] => 19483730 [patent_doc_number] => 20240331772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => CURRENT AND VOLTAGE LIMIT CIRCUITRY FOR RESISTIVE RANDOM ACCESS MEMORY PROGRAMMING [patent_app_type] => utility [patent_app_number] => 18/740981 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740981 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/740981
Current and voltage limit circuitry for resistive random access memory programming Jun 11, 2024 Issued
Array ( [id] => 20101769 [patent_doc_number] => 20250231705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => COARSE AND FINE PROGRAMMING OF NON-VOLATILE MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/648219 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18648219 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/648219
Coarse and fine programming of non-volatile memory cells Apr 25, 2024 Issued
Array ( [id] => 19544909 [patent_doc_number] => 20240361945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => INVERSE ERASE FOR MEMORY COMPONENTS [patent_app_type] => utility [patent_app_number] => 18/645713 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18645713 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/645713
INVERSE ERASE FOR MEMORY COMPONENTS Apr 24, 2024 Pending
Array ( [id] => 19544909 [patent_doc_number] => 20240361945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => INVERSE ERASE FOR MEMORY COMPONENTS [patent_app_type] => utility [patent_app_number] => 18/645713 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18645713 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/645713
INVERSE ERASE FOR MEMORY COMPONENTS Apr 24, 2024 Pending
Array ( [id] => 20109267 [patent_doc_number] => 12359978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Temperature exception tracking in a temperature log for a memory system [patent_app_type] => utility [patent_app_number] => 18/646587 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 13710 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646587 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/646587
Temperature exception tracking in a temperature log for a memory system Apr 24, 2024 Issued
Array ( [id] => 19544909 [patent_doc_number] => 20240361945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => INVERSE ERASE FOR MEMORY COMPONENTS [patent_app_type] => utility [patent_app_number] => 18/645713 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18645713 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/645713
INVERSE ERASE FOR MEMORY COMPONENTS Apr 24, 2024 Pending
Array ( [id] => 19559634 [patent_doc_number] => 20240371426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => Bank-Shared Usage-Based Disturbance Circuitry [patent_app_type] => utility [patent_app_number] => 18/635631 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8080 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635631 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635631
Bank-Shared Usage-Based Disturbance Circuitry Apr 14, 2024 Pending
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