
Pho M. Luu
Examiner (ID: 13870, Phone: (571)272-1876 , Office: P/2824 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2818, 2811, 2824 |
| Total Applications | 2531 |
| Issued Applications | 2381 |
| Pending Applications | 112 |
| Abandoned Applications | 66 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20028474
[patent_doc_number] => 20250166696
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-22
[patent_title] => MANAGEMENT OF DYNAMIC READ VOLTAGE SEQUENCES IN A MEMORY SUBSYSTEM
[patent_app_type] => utility
[patent_app_number] => 19/030522
[patent_app_country] => US
[patent_app_date] => 2025-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2319
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19030522
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/030522 | MANAGEMENT OF DYNAMIC READ VOLTAGE SEQUENCES IN A MEMORY SUBSYSTEM | Jan 16, 2025 | Pending |
Array
(
[id] => 20296640
[patent_doc_number] => 20250321883
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-16
[patent_title] => DYNAMIC VOLTAGE SUPPLY FOR MEMORY CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 19/017332
[patent_app_country] => US
[patent_app_date] => 2025-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10872
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19017332
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/017332 | DYNAMIC VOLTAGE SUPPLY FOR MEMORY CIRCUIT | Jan 9, 2025 | Pending |
Array
(
[id] => 20338777
[patent_doc_number] => 20250342897
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-11-06
[patent_title] => MEMORY DEVICE FOR COUNTING SEQUENCE OF OPERATION
[patent_app_type] => utility
[patent_app_number] => 19/013956
[patent_app_country] => US
[patent_app_date] => 2025-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6530
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19013956
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/013956 | MEMORY DEVICE FOR COUNTING SEQUENCE OF OPERATION | Jan 7, 2025 | Pending |
Array
(
[id] => 20681906
[patent_doc_number] => 20260120731
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-04-30
[patent_title] => Model Inversion in Integrated Circuit Devices having Analog Inference Capability
[patent_app_type] => utility
[patent_app_number] => 19/008342
[patent_app_country] => US
[patent_app_date] => 2025-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20941
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19008342
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/008342 | Model Inversion in Integrated Circuit Devices having Analog Inference Capability | Jan 1, 2025 | Pending |
Array
(
[id] => 19986749
[patent_doc_number] => 20250124971
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-17
[patent_title] => Single-Ended Sense Amplifiers And Methods For Operating Same
[patent_app_type] => utility
[patent_app_number] => 19/002313
[patent_app_country] => US
[patent_app_date] => 2024-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 24710
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -28
[patent_words_short_claim] => 239
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19002313
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/002313 | Single-Ended Sense Amplifiers And Methods For Operating Same | Dec 25, 2024 | Pending |
Array
(
[id] => 20196551
[patent_doc_number] => 20250273261
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-28
[patent_title] => TWO-TRANSISTOR DRAM CELL AND METHOD OF REFRESHING TWO-TRANSISTOR DRAM CELL
[patent_app_type] => utility
[patent_app_number] => 18/989799
[patent_app_country] => US
[patent_app_date] => 2024-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1332
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18989799
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/989799 | TWO-TRANSISTOR DRAM CELL AND METHOD OF REFRESHING TWO-TRANSISTOR DRAM CELL | Dec 19, 2024 | Pending |
Array
(
[id] => 19986948
[patent_doc_number] => 20250125170
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-17
[patent_title] => RECONFIGURABLE MAINFRAME WITH REPLACEABLE INTERFACE PLATE
[patent_app_type] => utility
[patent_app_number] => 18/991285
[patent_app_country] => US
[patent_app_date] => 2024-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3501
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18991285
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/991285 | RECONFIGURABLE MAINFRAME WITH REPLACEABLE INTERFACE PLATE | Dec 19, 2024 | Pending |
Array
(
[id] => 19986770
[patent_doc_number] => 20250124992
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-17
[patent_title] => ONE-TIME PROGRAMMABLE BITCELL FOR FRONTSIDE AND BACKSIDE POWER INTERCONNECT
[patent_app_type] => utility
[patent_app_number] => 18/991201
[patent_app_country] => US
[patent_app_date] => 2024-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5569
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18991201
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/991201 | ONE-TIME PROGRAMMABLE BITCELL FOR FRONTSIDE AND BACKSIDE POWER INTERCONNECT | Dec 19, 2024 | Pending |
Array
(
[id] => 19986763
[patent_doc_number] => 20250124985
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-17
[patent_title] => STORAGE SYSTEM AND OPERATING METHOD OF STORAGE CONTROLLER
[patent_app_type] => utility
[patent_app_number] => 18/988592
[patent_app_country] => US
[patent_app_date] => 2024-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4618
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18988592
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/988592 | STORAGE SYSTEM AND OPERATING METHOD OF STORAGE CONTROLLER | Dec 18, 2024 | Pending |
Array
(
[id] => 19865986
[patent_doc_number] => 20250104772
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-27
[patent_title] => MEMORY CELL VOLTAGE LEVEL SELECTION
[patent_app_type] => utility
[patent_app_number] => 18/971520
[patent_app_country] => US
[patent_app_date] => 2024-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9899
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18971520
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/971520 | MEMORY CELL VOLTAGE LEVEL SELECTION | Dec 5, 2024 | Pending |
Array
(
[id] => 20096085
[patent_doc_number] => 20250226021
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-10
[patent_title] => EDRAM CELL AND COMPUTE-IN-MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/963479
[patent_app_country] => US
[patent_app_date] => 2024-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18963479
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/963479 | EDRAM CELL AND COMPUTE-IN-MEMORY DEVICE | Nov 26, 2024 | Pending |
Array
(
[id] => 19851705
[patent_doc_number] => 20250097056
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-20
[patent_title] => NOVEL PUF GENERATORS BASED ON SRAM BIT CELLS
[patent_app_type] => utility
[patent_app_number] => 18/961173
[patent_app_country] => US
[patent_app_date] => 2024-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 21228
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18961173
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/961173 | NOVEL PUF GENERATORS BASED ON SRAM BIT CELLS | Nov 25, 2024 | Pending |
Array
(
[id] => 20071855
[patent_doc_number] => 20250210077
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-26
[patent_title] => DECISION FEEDBACK EQUALIZER, AND MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/955883
[patent_app_country] => US
[patent_app_date] => 2024-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6530
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18955883
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/955883 | DECISION FEEDBACK EQUALIZER, AND MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME | Nov 20, 2024 | Pending |
Array
(
[id] => 20182109
[patent_doc_number] => 20250266067
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-21
[patent_title] => MEMORY CONTROLLER COMMUNICATING WITH VERTICALLY STACKED DIES AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/955618
[patent_app_country] => US
[patent_app_date] => 2024-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4948
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18955618
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/955618 | MEMORY CONTROLLER COMMUNICATING WITH VERTICALLY STACKED DIES AND SEMICONDUCTOR DEVICE INCLUDING THE SAME | Nov 20, 2024 | Pending |
Array
(
[id] => 19820671
[patent_doc_number] => 20250078878
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-06
[patent_title] => MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/952783
[patent_app_country] => US
[patent_app_date] => 2024-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9560
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18952783
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/952783 | MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME | Nov 18, 2024 | Pending |
Array
(
[id] => 20088580
[patent_doc_number] => 20250218516
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-03
[patent_title] => MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/952707
[patent_app_country] => US
[patent_app_date] => 2024-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11555
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 278
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18952707
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/952707 | MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY DEVICE | Nov 18, 2024 | Pending |
Array
(
[id] => 19803726
[patent_doc_number] => 20250069651
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-27
[patent_title] => BISTABLE CIRCUIT AND ELECTRONIC CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 18/947451
[patent_app_country] => US
[patent_app_date] => 2024-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 41220
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18947451
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/947451 | BISTABLE CIRCUIT AND ELECTRONIC CIRCUIT | Nov 13, 2024 | Pending |
Array
(
[id] => 19803728
[patent_doc_number] => 20250069653
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-27
[patent_title] => COMPUTING-IN-MEMORY CIRCUIT AND SRAM MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/947250
[patent_app_country] => US
[patent_app_date] => 2024-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9349
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18947250
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/947250 | COMPUTING-IN-MEMORY CIRCUIT AND SRAM MEMORY DEVICE | Nov 13, 2024 | Pending |
Array
(
[id] => 19790114
[patent_doc_number] => 20250063793
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-20
[patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND ASSOCIATED MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/937075
[patent_app_country] => US
[patent_app_date] => 2024-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5964
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18937075
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/937075 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND ASSOCIATED MEMORY DEVICE | Nov 4, 2024 | Pending |
Array
(
[id] => 20250873
[patent_doc_number] => 20250299742
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-25
[patent_title] => DATA STORAGE DEVICE WHICH ERASES BY GROUPING MEMORY BLOCKS AND METHOD OF OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/935651
[patent_app_country] => US
[patent_app_date] => 2024-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 905
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18935651
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/935651 | DATA STORAGE DEVICE WHICH ERASES BY GROUPING MEMORY BLOCKS AND METHOD OF OPERATING THE SAME | Nov 3, 2024 | Pending |