
Pho M. Luu
Examiner (ID: 19321, Phone: (571)272-1876 , Office: P/2824 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2818, 2824, 2811 |
| Total Applications | 2492 |
| Issued Applications | 2364 |
| Pending Applications | 99 |
| Abandoned Applications | 66 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19500143
[patent_doc_number] => 20240339161
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-10
[patent_title] => NON-VOLATILE MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/749001
[patent_app_country] => US
[patent_app_date] => 2024-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6182
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749001
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/749001 | NON-VOLATILE MEMORY DEVICE | Jun 19, 2024 | Pending |
Array
(
[id] => 19694713
[patent_doc_number] => 20250013258
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-09
[patent_title] => SYSTEMS AND TECHNIQUES FOR CLOCK DOUBLING
[patent_app_type] => utility
[patent_app_number] => 18/749057
[patent_app_country] => US
[patent_app_date] => 2024-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12812
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749057
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/749057 | SYSTEMS AND TECHNIQUES FOR CLOCK DOUBLING | Jun 19, 2024 | Pending |
Array
(
[id] => 19500142
[patent_doc_number] => 20240339160
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-10
[patent_title] => SEMICONDUCTOR MEMORY AND NONVOLATILE MEMORY
[patent_app_type] => utility
[patent_app_number] => 18/746964
[patent_app_country] => US
[patent_app_date] => 2024-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 51231
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 363
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746964
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/746964 | SEMICONDUCTOR MEMORY AND NONVOLATILE MEMORY | Jun 17, 2024 | Pending |
Array
(
[id] => 19486798
[patent_doc_number] => 20240334840
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => MAGNETIC TUNNELING JUNCTION DEVICE AND MEMORY DEVICE INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/742115
[patent_app_country] => US
[patent_app_date] => 2024-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8670
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742115
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/742115 | MAGNETIC TUNNELING JUNCTION DEVICE AND MEMORY DEVICE INCLUDING THE SAME | Jun 12, 2024 | Pending |
Array
(
[id] => 19483730
[patent_doc_number] => 20240331772
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => CURRENT AND VOLTAGE LIMIT CIRCUITRY FOR RESISTIVE RANDOM ACCESS MEMORY PROGRAMMING
[patent_app_type] => utility
[patent_app_number] => 18/740981
[patent_app_country] => US
[patent_app_date] => 2024-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3678
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740981
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/740981 | Current and voltage limit circuitry for resistive random access memory programming | Jun 11, 2024 | Issued |
Array
(
[id] => 20323029
[patent_doc_number] => 20250335117
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-30
[patent_title] => WRITE DATA PATH FOR HIGH-SPEED TIME-SHARED SERIAL READ WRITE MEMORIES HAVING WRITE MASK
[patent_app_type] => utility
[patent_app_number] => 18/648222
[patent_app_country] => US
[patent_app_date] => 2024-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5093
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18648222
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/648222 | WRITE DATA PATH FOR HIGH-SPEED TIME-SHARED SERIAL READ WRITE MEMORIES HAVING WRITE MASK | Apr 25, 2024 | Pending |
Array
(
[id] => 20101769
[patent_doc_number] => 20250231705
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-17
[patent_title] => COARSE AND FINE PROGRAMMING OF NON-VOLATILE MEMORY CELLS
[patent_app_type] => utility
[patent_app_number] => 18/648219
[patent_app_country] => US
[patent_app_date] => 2024-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18648219
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/648219 | Coarse and fine programming of non-volatile memory cells | Apr 25, 2024 | Issued |
Array
(
[id] => 20109267
[patent_doc_number] => 12359978
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-15
[patent_title] => Temperature exception tracking in a temperature log for a memory system
[patent_app_type] => utility
[patent_app_number] => 18/646587
[patent_app_country] => US
[patent_app_date] => 2024-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 13710
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646587
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/646587 | Temperature exception tracking in a temperature log for a memory system | Apr 24, 2024 | Issued |
Array
(
[id] => 19544909
[patent_doc_number] => 20240361945
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-31
[patent_title] => INVERSE ERASE FOR MEMORY COMPONENTS
[patent_app_type] => utility
[patent_app_number] => 18/645713
[patent_app_country] => US
[patent_app_date] => 2024-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7021
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18645713
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/645713 | INVERSE ERASE FOR MEMORY COMPONENTS | Apr 24, 2024 | Pending |
Array
(
[id] => 19559634
[patent_doc_number] => 20240371426
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-07
[patent_title] => Bank-Shared Usage-Based Disturbance Circuitry
[patent_app_type] => utility
[patent_app_number] => 18/635631
[patent_app_country] => US
[patent_app_date] => 2024-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8080
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635631
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/635631 | Bank-Shared Usage-Based Disturbance Circuitry | Apr 14, 2024 | Pending |
Array
(
[id] => 20297619
[patent_doc_number] => 20250322862
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-16
[patent_title] => AP-pinned Data Storage Layer and Laminated Topological Heusler Alloy SOT-MRAM Unit Cell for In-Memory Computing Artificial Intelligence Inference Chip
[patent_app_type] => utility
[patent_app_number] => 18/633153
[patent_app_country] => US
[patent_app_date] => 2024-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18633153
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/633153 | AP-pinned Data Storage Layer and Laminated Topological Heusler Alloy SOT-MRAM Unit Cell for In-Memory Computing Artificial Intelligence Inference Chip | Apr 10, 2024 | Pending |
Array
(
[id] => 19335343
[patent_doc_number] => 20240249773
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-25
[patent_title] => NON-VOLATILE MEMORY AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/625956
[patent_app_country] => US
[patent_app_date] => 2024-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7014
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625956
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/625956 | Non-volatile memory and operating method thereof | Apr 2, 2024 | Issued |
Array
(
[id] => 20281559
[patent_doc_number] => 20250306801
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-02
[patent_title] => SELECT GATE BIAS GRADATION STRUCTURE IN NAND MEMORY
[patent_app_type] => utility
[patent_app_number] => 18/624399
[patent_app_country] => US
[patent_app_date] => 2024-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13120
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 224
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624399
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/624399 | Select gate bias gradation structure in NAND memory | Apr 1, 2024 | Issued |
Array
(
[id] => 20080626
[patent_doc_number] => 12354701
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-08
[patent_title] => Sense amplifier circuit and method
[patent_app_type] => utility
[patent_app_number] => 18/615497
[patent_app_country] => US
[patent_app_date] => 2024-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 1068
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18615497
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/615497 | Sense amplifier circuit and method | Mar 24, 2024 | Issued |
Array
(
[id] => 19481798
[patent_doc_number] => 20240329840
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => MEMORY ARRAY CONFIGURATION FOR SHARED WORD LINES
[patent_app_type] => utility
[patent_app_number] => 18/607026
[patent_app_country] => US
[patent_app_date] => 2024-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17303
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18607026
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/607026 | MEMORY ARRAY CONFIGURATION FOR SHARED WORD LINES | Mar 14, 2024 | Pending |
Array
(
[id] => 19470499
[patent_doc_number] => 20240324169
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/601832
[patent_app_country] => US
[patent_app_date] => 2024-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20573
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18601832
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/601832 | MEMORY DEVICE | Mar 10, 2024 | Pending |
Array
(
[id] => 20080570
[patent_doc_number] => 12354645
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-08
[patent_title] => Memory with artificial intelligence mode
[patent_app_type] => utility
[patent_app_number] => 18/594666
[patent_app_country] => US
[patent_app_date] => 2024-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 10801
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594666
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/594666 | Memory with artificial intelligence mode | Mar 3, 2024 | Issued |
Array
(
[id] => 19321216
[patent_doc_number] => 20240242762
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-18
[patent_title] => Bit Line Pre-Charge Circuit for Power Management Modes in Multi Bank SRAM
[patent_app_type] => utility
[patent_app_number] => 18/585184
[patent_app_country] => US
[patent_app_date] => 2024-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8330
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18585184
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/585184 | Bit line pre-charge circuit for power management modes in multi bank SRAM | Feb 22, 2024 | Issued |
Array
(
[id] => 19237090
[patent_doc_number] => 20240194285
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-13
[patent_title] => MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/583294
[patent_app_country] => US
[patent_app_date] => 2024-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5664
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583294
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/583294 | MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME | Feb 20, 2024 | Pending |
Array
(
[id] => 20181057
[patent_doc_number] => 20250265015
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-21
[patent_title] => FPGA MEMORY WITH AUTO ADDRESS MODE
[patent_app_type] => utility
[patent_app_number] => 18/581131
[patent_app_country] => US
[patent_app_date] => 2024-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1160
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581131
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/581131 | FPGA MEMORY WITH AUTO ADDRESS MODE | Feb 18, 2024 | Pending |