
Pho M. Luu
Examiner (ID: 13870, Phone: (571)272-1876 , Office: P/2824 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2818, 2811, 2824 |
| Total Applications | 2531 |
| Issued Applications | 2381 |
| Pending Applications | 112 |
| Abandoned Applications | 66 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
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