Search

Phong Son H. Dang

Examiner (ID: 488, Phone: (571)270-5809 , Office: P/3731 )

Most Active Art Unit
3771
Art Unit(s)
3771, 3773, 3731
Total Applications
1074
Issued Applications
866
Pending Applications
62
Abandoned Applications
178

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19560222 [patent_doc_number] => 20240372014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => SEMICONDUCTOR TRENCH CAPACITOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/779095 [patent_app_country] => US [patent_app_date] => 2024-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18779095 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/779095
SEMICONDUCTOR TRENCH CAPACITOR STRUCTURE AND MANUFACTURING METHOD THEREOF Jul 21, 2024 Pending
Array ( [id] => 19531969 [patent_doc_number] => 20240355871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => SEMICONDUCTOR STRUCTURES HAVING DEEP TRENCH CAPACITOR AND METHODS FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/763075 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763075 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763075
Semiconductor structures having deep trench capacitor and methods for manufacturing the same Jul 2, 2024 Issued
Array ( [id] => 20347561 [patent_doc_number] => 12471299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Ferroelectric tunnel junction devices with a sparse seed layer and methods for forming the same [patent_app_type] => utility [patent_app_number] => 18/755379 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 28 [patent_no_of_words] => 5510 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18755379 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/755379
Ferroelectric tunnel junction devices with a sparse seed layer and methods for forming the same Jun 25, 2024 Issued
Array ( [id] => 20347561 [patent_doc_number] => 12471299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Ferroelectric tunnel junction devices with a sparse seed layer and methods for forming the same [patent_app_type] => utility [patent_app_number] => 18/755379 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 28 [patent_no_of_words] => 5510 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18755379 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/755379
Ferroelectric tunnel junction devices with a sparse seed layer and methods for forming the same Jun 25, 2024 Issued
Array ( [id] => 19500501 [patent_doc_number] => 20240339519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => SEMICONDUCTOR DEVICE, FERROELECTRIC CAPACITOR AND LAMINATED STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/747379 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6032 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18747379 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/747379
Semiconductor device, ferroelectric capacitor and laminated structure Jun 17, 2024 Issued
Array ( [id] => 19484305 [patent_doc_number] => 20240332347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => SEMICONDUCTOR STRUCTURES HAVING DEEP TRENCH CAPACITOR AND METHODS FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/743431 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10333 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18743431 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/743431
Semiconductor structures having deep trench capacitor and methods for manufacturing the same Jun 13, 2024 Issued
Array ( [id] => 19468340 [patent_doc_number] => 20240322010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => REDUCING PATTERN LOADING IN THE ETCH-BACK OF METAL GATE [patent_app_type] => utility [patent_app_number] => 18/731945 [patent_app_country] => US [patent_app_date] => 2024-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7854 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18731945 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/731945
REDUCING PATTERN LOADING IN THE ETCH-BACK OF METAL GATE Jun 2, 2024 Pending
Array ( [id] => 20146789 [patent_doc_number] => 12381136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Lead frame and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/678270 [patent_app_country] => US [patent_app_date] => 2024-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 157 [patent_no_of_words] => 35183 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18678270 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/678270
Lead frame and manufacturing method thereof May 29, 2024 Issued
Array ( [id] => 19452654 [patent_doc_number] => 20240312784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE INCLUDING A MOS TRANSISTOR HAVING A SILICIDE LAYER [patent_app_type] => utility [patent_app_number] => 18/674923 [patent_app_country] => US [patent_app_date] => 2024-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6844 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18674923 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/674923
Method for fabricating a semiconductor device including a MOS transistor having a silicide layer May 26, 2024 Issued
Array ( [id] => 19452654 [patent_doc_number] => 20240312784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE INCLUDING A MOS TRANSISTOR HAVING A SILICIDE LAYER [patent_app_type] => utility [patent_app_number] => 18/674923 [patent_app_country] => US [patent_app_date] => 2024-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6844 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18674923 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/674923
Method for fabricating a semiconductor device including a MOS transistor having a silicide layer May 26, 2024 Issued
Array ( [id] => 19437895 [patent_doc_number] => 20240306393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/666035 [patent_app_country] => US [patent_app_date] => 2024-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18666035 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/666035
Semiconductor memory device May 15, 2024 Issued
Array ( [id] => 19422324 [patent_doc_number] => 20240298448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, MEMORY DEVICE, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/659523 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18659523 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/659523
Semiconductor device, semiconductor wafer, memory device, and electronic device May 8, 2024 Issued
Array ( [id] => 19709087 [patent_doc_number] => 20250019229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => STACKED-DIE MEMS RESONATOR [patent_app_type] => utility [patent_app_number] => 18/641815 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18641815 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/641815
MEMS resonator integrated cicruit fabrication Apr 21, 2024 Issued
Array ( [id] => 19705092 [patent_doc_number] => 12199140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Semiconductor device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/614757 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12048 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614757 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614757
Semiconductor device and method for manufacturing the same Mar 24, 2024 Issued
Array ( [id] => 19269672 [patent_doc_number] => 20240213377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => TRENCH CAPACITOR STRUCTURE WITH HYBRID FILLING LAYER [patent_app_type] => utility [patent_app_number] => 18/594215 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7489 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594215 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/594215
Trench capacitor structure with hybrid filling layer Mar 3, 2024 Issued
Array ( [id] => 19269672 [patent_doc_number] => 20240213377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => TRENCH CAPACITOR STRUCTURE WITH HYBRID FILLING LAYER [patent_app_type] => utility [patent_app_number] => 18/594215 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7489 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594215 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/594215
Trench capacitor structure with hybrid filling layer Mar 3, 2024 Issued
Array ( [id] => 19335750 [patent_doc_number] => 20240250180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => THIN FILM TRANSISTOR AND VERTICAL NON-VOLATILE MEMORY DEVICE INCLUDING TRANSITION METAL-INDUCED POLYCRYSTALLINE METAL OXIDE CHANNEL LAYER [patent_app_type] => utility [patent_app_number] => 18/586255 [patent_app_country] => US [patent_app_date] => 2024-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10421 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18586255 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/586255
Thin film transistor and vertical non-volatile memory device including transition metal-induced polycrystalline metal oxide channel layer Feb 22, 2024 Issued
Array ( [id] => 19221665 [patent_doc_number] => 20240186369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => INTEGRATED CIRCUIT DEVICES AND METHODS OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/439785 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11575 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18439785 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/439785
Integrated circuit devices and methods of manufacturing the same Feb 12, 2024 Issued
Array ( [id] => 19221588 [patent_doc_number] => 20240186292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => Semiconductor Package Using A Coreless Signal Distribution Structure [patent_app_type] => utility [patent_app_number] => 18/406403 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7809 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406403 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406403
Semiconductor package using a coreless signal distribution structure Jan 7, 2024 Issued
Array ( [id] => 19161280 [patent_doc_number] => 20240153987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => MULTI-LAYER TRENCH CAPACITOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/405134 [patent_app_country] => US [patent_app_date] => 2024-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9366 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18405134 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/405134
Multi-layer trench capacitor structure Jan 4, 2024 Issued
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