Search

Phung M. Chung

Examiner (ID: 17124, Phone: (571)272-3818 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2413, 2138, 2306, 2784, 2133, 2111, 2117, 2785, 2313
Total Applications
1956
Issued Applications
1779
Pending Applications
38
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11584780 [patent_doc_number] => 09639422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-02 [patent_title] => 'Synchronized transfer of data and corresponding error correction data' [patent_app_type] => utility [patent_app_number] => 15/072572 [patent_app_country] => US [patent_app_date] => 2016-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5430 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15072572 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/072572
Synchronized transfer of data and corresponding error correction data Mar 16, 2016 Issued
Array ( [id] => 11591657 [patent_doc_number] => 20170116068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'REPORTING ERRORS TO A DATA STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 15/051636 [patent_app_country] => US [patent_app_date] => 2016-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6713 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15051636 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/051636
Reporting errors to a data storage device Feb 22, 2016 Issued
Array ( [id] => 13893111 [patent_doc_number] => 10199107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Data storage device and data refresh method thereof [patent_app_type] => utility [patent_app_number] => 14/997916 [patent_app_country] => US [patent_app_date] => 2016-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4829 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14997916 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/997916
Data storage device and data refresh method thereof Jan 17, 2016 Issued
Array ( [id] => 11759262 [patent_doc_number] => 20170206131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'NON-VOLATILE MEMORY INCLUDING SELECTIVE ERROR CORRECTION' [patent_app_type] => utility [patent_app_number] => 14/997164 [patent_app_country] => US [patent_app_date] => 2016-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7468 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14997164 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/997164
Non-volatile memory including selective error correction Jan 14, 2016 Issued
Array ( [id] => 11086360 [patent_doc_number] => 20160283326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'DATA PROCESSING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/995985 [patent_app_country] => US [patent_app_date] => 2016-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 15557 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14995985 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/995985
Data processing circuit Jan 13, 2016 Issued
Array ( [id] => 13083155 [patent_doc_number] => 10061644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-28 [patent_title] => Systems and methods for implementing error correcting code in a memory [patent_app_type] => utility [patent_app_number] => 14/994078 [patent_app_country] => US [patent_app_date] => 2016-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12594 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14994078 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/994078
Systems and methods for implementing error correcting code in a memory Jan 11, 2016 Issued
Array ( [id] => 11745702 [patent_doc_number] => 20170199775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-13 [patent_title] => 'ESTIMATION OF ERROR CORRECTING PERFORMANCE OF LOW-DENSITY PARITY-CHECK (LDPC) CODES' [patent_app_type] => utility [patent_app_number] => 14/992657 [patent_app_country] => US [patent_app_date] => 2016-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7521 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14992657 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/992657
Estimation of error correcting performance of low-density parity-check (LDPC) codes Jan 10, 2016 Issued
Array ( [id] => 11651529 [patent_doc_number] => 20170147430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'METHODS AND APPARATUS TO DETECT AND CORRECT ERRORS IN DESTRUCTIVE READ NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/989293 [patent_app_country] => US [patent_app_date] => 2016-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10583 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14989293 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/989293
METHODS AND APPARATUS TO DETECT AND CORRECT ERRORS IN DESTRUCTIVE READ NON-VOLATILE MEMORY Jan 5, 2016 Abandoned
Array ( [id] => 11000677 [patent_doc_number] => 20160197624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-07 [patent_title] => 'RELIABILITY-ASSISTED BIT-FLIPPING DECODING ALGORITHM' [patent_app_type] => utility [patent_app_number] => 14/988303 [patent_app_country] => US [patent_app_date] => 2016-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4764 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14988303 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/988303
Reliability-assisted bit-flipping decoding algorithm Jan 4, 2016 Issued
Array ( [id] => 11056279 [patent_doc_number] => 20160253240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'REBUILDING ENCODED DATA SLICES IN A DISPERSED STORAGE NETWORK' [patent_app_type] => utility [patent_app_number] => 14/984024 [patent_app_country] => US [patent_app_date] => 2015-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 58 [patent_no_of_words] => 41562 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14984024 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/984024
Rebuilding encoded data slices in a dispersed storage network Dec 29, 2015 Issued
Array ( [id] => 13201445 [patent_doc_number] => 10115643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Circuit and method for monolithic stacked integrated circuit testing [patent_app_type] => utility [patent_app_number] => 14/981604 [patent_app_country] => US [patent_app_date] => 2015-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 32 [patent_no_of_words] => 8555 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14981604 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/981604
Circuit and method for monolithic stacked integrated circuit testing Dec 27, 2015 Issued
Array ( [id] => 10765914 [patent_doc_number] => 20160112069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'Methods and Apparatus in Alternate Finite Field Based Coders and Decoders' [patent_app_type] => utility [patent_app_number] => 14/975841 [patent_app_country] => US [patent_app_date] => 2015-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 34715 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14975841 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/975841
Methods and Apparatus in Alternate Finite Field Based Coders and Decoders Dec 19, 2015 Abandoned
Array ( [id] => 13171901 [patent_doc_number] => 10102065 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-16 [patent_title] => Localized failure mode decorrelation in redundancy encoded data storage systems [patent_app_type] => utility [patent_app_number] => 14/973718 [patent_app_country] => US [patent_app_date] => 2015-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14637 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14973718 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/973718
Localized failure mode decorrelation in redundancy encoded data storage systems Dec 16, 2015 Issued
Array ( [id] => 13710493 [patent_doc_number] => 20170366201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => LOW-DENSITY PARITY CHECK DECODING [patent_app_type] => utility [patent_app_number] => 15/525485 [patent_app_country] => US [patent_app_date] => 2015-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6696 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15525485 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/525485
Low-density parity check decoding Nov 17, 2015 Issued
Array ( [id] => 10795919 [patent_doc_number] => 20160142076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'SYSTEM AND METHOD FOR IMPROVED DECODING USING IDENTIFIED RECURRING SIDE INFORMATION' [patent_app_type] => utility [patent_app_number] => 14/926653 [patent_app_country] => US [patent_app_date] => 2015-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6519 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14926653 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/926653
System and method for improved decoding using identified recurring side information Oct 28, 2015 Issued
Array ( [id] => 13891537 [patent_doc_number] => 10198316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Systems and methods for efficient flash memory access [patent_app_type] => utility [patent_app_number] => 14/925688 [patent_app_country] => US [patent_app_date] => 2015-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 10339 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14925688 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/925688
Systems and methods for efficient flash memory access Oct 27, 2015 Issued
Array ( [id] => 11606599 [patent_doc_number] => 20170123901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'Systems and Methods for Side Data Based Soft Data Flash Memory Access' [patent_app_type] => utility [patent_app_number] => 14/925755 [patent_app_country] => US [patent_app_date] => 2015-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14466 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14925755 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/925755
Systems and methods for side data based soft data flash memory access Oct 27, 2015 Issued
Array ( [id] => 11608949 [patent_doc_number] => 20170126255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'DYNAMICALLY ADJUSTING AN ERROR CORRECTION EFFORT LEVEL OF A STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 14/925255 [patent_app_country] => US [patent_app_date] => 2015-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6464 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14925255 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/925255
Dynamic error processing in a storage device Oct 27, 2015 Issued
Array ( [id] => 11591650 [patent_doc_number] => 20170116060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'ERROR LOCATION POINTERS FOR NVM' [patent_app_type] => utility [patent_app_number] => 14/924671 [patent_app_country] => US [patent_app_date] => 2015-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4522 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14924671 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/924671
Error location pointers for non volatile memory Oct 26, 2015 Issued
Array ( [id] => 13171899 [patent_doc_number] => 10102064 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-16 [patent_title] => Two layer quad bit error correction [patent_app_type] => utility [patent_app_number] => 14/923565 [patent_app_country] => US [patent_app_date] => 2015-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9196 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14923565 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/923565
Two layer quad bit error correction Oct 26, 2015 Issued
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