Search

Phung M. Chung

Examiner (ID: 7431, Phone: (571)272-3818 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2111, 2413, 2117, 2138, 2785, 2133, 2313, 2306, 2784
Total Applications
1956
Issued Applications
1779
Pending Applications
38
Abandoned Applications
145

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16324913 [patent_doc_number] => 10784894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 4/15 and 256-symbol mapping, and bit interleaving method using same [patent_app_type] => utility [patent_app_number] => 16/233596 [patent_app_country] => US [patent_app_date] => 2018-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5774 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16233596 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/233596
Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 4/15 and 256-symbol mapping, and bit interleaving method using same Dec 26, 2018 Issued
Array ( [id] => 14189033 [patent_doc_number] => 20190114222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => SELF-ACCUMULATING EXCLUSIVE OR PROGRAM [patent_app_type] => utility [patent_app_number] => 16/229578 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5532 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16229578 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/229578
Self-accumulating exclusive or program Dec 20, 2018 Issued
Array ( [id] => 16705544 [patent_doc_number] => 10955470 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-23 [patent_title] => Method to improve testability using 2-dimensional exclusive or (XOR) grids [patent_app_type] => utility [patent_app_number] => 16/218954 [patent_app_country] => US [patent_app_date] => 2018-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6389 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16218954 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/218954
Method to improve testability using 2-dimensional exclusive or (XOR) grids Dec 12, 2018 Issued
Array ( [id] => 16433601 [patent_doc_number] => 10833704 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-10 [patent_title] => Low-density parity check decoder using encoded no-operation instructions [patent_app_type] => utility [patent_app_number] => 16/217648 [patent_app_country] => US [patent_app_date] => 2018-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 16030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16217648 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/217648
Low-density parity check decoder using encoded no-operation instructions Dec 11, 2018 Issued
Array ( [id] => 16339071 [patent_doc_number] => 10790038 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => Semiconductor apparatus and test system including the semiconductor apparatus [patent_app_type] => utility [patent_app_number] => 16/216748 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5053 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16216748 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/216748
Semiconductor apparatus and test system including the semiconductor apparatus Dec 10, 2018 Issued
Array ( [id] => 17121119 [patent_doc_number] => 11132253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => Direct-input redundancy scheme with dedicated error correction code circuit [patent_app_type] => utility [patent_app_number] => 16/211980 [patent_app_country] => US [patent_app_date] => 2018-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 19015 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16211980 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/211980
Direct-input redundancy scheme with dedicated error correction code circuit Dec 5, 2018 Issued
Array ( [id] => 16281732 [patent_doc_number] => 10764786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Machine learning between radio loading and user experience [patent_app_type] => utility [patent_app_number] => 16/210518 [patent_app_country] => US [patent_app_date] => 2018-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12412 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16210518 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/210518
Machine learning between radio loading and user experience Dec 4, 2018 Issued
Array ( [id] => 16017871 [patent_doc_number] => 20200183779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => NAND DEVICE MIXED PARITY MANAGEMENT [patent_app_type] => utility [patent_app_number] => 16/210730 [patent_app_country] => US [patent_app_date] => 2018-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11365 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16210730 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/210730
NAND device mixed parity management Dec 4, 2018 Issued
Array ( [id] => 16683184 [patent_doc_number] => 10942661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-09 [patent_title] => Non-volatile memory including selective error correction [patent_app_type] => utility [patent_app_number] => 16/196304 [patent_app_country] => US [patent_app_date] => 2018-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7120 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16196304 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/196304
Non-volatile memory including selective error correction Nov 19, 2018 Issued
Array ( [id] => 14986765 [patent_doc_number] => 10447308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 3/15 and 256-symbol mapping, and bit interleaving method using same [patent_app_type] => utility [patent_app_number] => 16/192544 [patent_app_country] => US [patent_app_date] => 2018-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5875 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16192544 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/192544
Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 3/15 and 256-symbol mapping, and bit interleaving method using same Nov 14, 2018 Issued
Array ( [id] => 16927090 [patent_doc_number] => 11048573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Data processing system and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/189984 [patent_app_country] => US [patent_app_date] => 2018-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8744 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16189984 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/189984
Data processing system and operating method thereof Nov 12, 2018 Issued
Array ( [id] => 15669015 [patent_doc_number] => 10598730 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-24 [patent_title] => Testing method and testing system [patent_app_type] => utility [patent_app_number] => 16/188699 [patent_app_country] => US [patent_app_date] => 2018-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3981 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16188699 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/188699
Testing method and testing system Nov 12, 2018 Issued
Array ( [id] => 15903095 [patent_doc_number] => 20200151067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => HIGH-RELIABILITY NON-VOLATILE MEMORY USING A VOTING MECHANISM [patent_app_type] => utility [patent_app_number] => 16/189697 [patent_app_country] => US [patent_app_date] => 2018-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9674 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16189697 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/189697
High-reliability non-volatile memory using a voting mechanism Nov 12, 2018 Issued
Array ( [id] => 16926435 [patent_doc_number] => 11047910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Path based controls for ATE mode testing of multicell memory circuit [patent_app_type] => utility [patent_app_number] => 16/185660 [patent_app_country] => US [patent_app_date] => 2018-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3982 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16185660 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/185660
Path based controls for ATE mode testing of multicell memory circuit Nov 8, 2018 Issued
Array ( [id] => 15820711 [patent_doc_number] => 10635535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Semiconductor memory devices, memory systems, and methods of operating the semiconductor memory devices [patent_app_type] => utility [patent_app_number] => 16/185453 [patent_app_country] => US [patent_app_date] => 2018-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 8539 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16185453 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/185453
Semiconductor memory devices, memory systems, and methods of operating the semiconductor memory devices Nov 8, 2018 Issued
Array ( [id] => 14541771 [patent_doc_number] => 20190206507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => DYNAMIC GENERATION OF ATPG MODE SIGNALS FOR TESTING MULTIPATH MEMORY CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/185629 [patent_app_country] => US [patent_app_date] => 2018-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4269 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16185629 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/185629
Dynamic generation of ATPG mode signals for testing multipath memory circuit Nov 8, 2018 Issued
Array ( [id] => 16418739 [patent_doc_number] => 10826651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Data sending method, data receiving method, sending device, and receiving device [patent_app_type] => utility [patent_app_number] => 16/183187 [patent_app_country] => US [patent_app_date] => 2018-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 10614 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16183187 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/183187
Data sending method, data receiving method, sending device, and receiving device Nov 6, 2018 Issued
Array ( [id] => 17046569 [patent_doc_number] => 11099749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Erase detection logic for a storage system [patent_app_type] => utility [patent_app_number] => 16/167383 [patent_app_country] => US [patent_app_date] => 2018-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 8898 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16167383 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/167383
Erase detection logic for a storage system Oct 21, 2018 Issued
Array ( [id] => 16036445 [patent_doc_number] => 10680659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => System and method for improved decoding using identified recurring side information [patent_app_type] => utility [patent_app_number] => 16/154001 [patent_app_country] => US [patent_app_date] => 2018-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6482 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16154001 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/154001
System and method for improved decoding using identified recurring side information Oct 7, 2018 Issued
Array ( [id] => 17422458 [patent_doc_number] => 11255905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Fault tolerant synchronizer [patent_app_type] => utility [patent_app_number] => 16/152531 [patent_app_country] => US [patent_app_date] => 2018-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3762 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16152531 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/152531
Fault tolerant synchronizer Oct 4, 2018 Issued
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