Array
(
[id] => 3708453
[patent_doc_number] => 05619665
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-08
[patent_title] => 'Method and apparatus for the transparent emulation of an existing instruction-set architecture by an arbitrary underlying instruction-set architecture'
[patent_app_type] => 1
[patent_app_number] => 8/421344
[patent_app_country] => US
[patent_app_date] => 1995-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 7834
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/619/05619665.pdf
[firstpage_image] =>[orig_patent_app_number] => 421344
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/421344 | Method and apparatus for the transparent emulation of an existing instruction-set architecture by an arbitrary underlying instruction-set architecture | Apr 12, 1995 | Issued |
Array
(
[id] => 3667135
[patent_doc_number] => 05623614
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-22
[patent_title] => 'Branch prediction cache with multiple entries for returns having multiple callers'
[patent_app_type] => 1
[patent_app_number] => 8/122922
[patent_app_country] => US
[patent_app_date] => 1993-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6801
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/623/05623614.pdf
[firstpage_image] =>[orig_patent_app_number] => 122922
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/122922 | Branch prediction cache with multiple entries for returns having multiple callers | Sep 16, 1993 | Issued |