Application number | Title of the application | Filing Date | Status |
---|
Array
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[patent_kind] => NA
[patent_issue_date] => 1993-09-21
[patent_title] => 'Method of virtual memory storage allocation with dynamic adjustment'
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[patent_app_number] => 7/379257
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[patent_app_date] => 1989-07-13
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Array
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[patent_kind] => NA
[patent_issue_date] => 1994-03-22
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[firstpage_image] =>[orig_patent_app_number] => 370341
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/370341 | Shared memory multiprocessor system and method of operation thereof | Jun 21, 1989 | Issued |
Array
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[id] => 2998743
[patent_doc_number] => 05251308
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-05
[patent_title] => 'Shared memory multiprocessor with data hiding and post-store'
[patent_app_type] => 1
[patent_app_number] => 7/370287
[patent_app_country] => US
[patent_app_date] => 1989-06-22
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/370287 | Shared memory multiprocessor with data hiding and post-store | Jun 21, 1989 | Issued |
Array
(
[id] => 2892433
[patent_doc_number] => 05109489
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-28
[patent_title] => 'I/O execution method for a virtual machine system and system therefor'
[patent_app_type] => 1
[patent_app_number] => 7/369535
[patent_app_country] => US
[patent_app_date] => 1989-06-21
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/369535 | I/O execution method for a virtual machine system and system therefor | Jun 20, 1989 | Issued |
Array
(
[id] => 2889525
[patent_doc_number] => 05159667
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-27
[patent_title] => 'Document identification by characteristics matching'
[patent_app_type] => 1
[patent_app_number] => 7/359839
[patent_app_country] => US
[patent_app_date] => 1989-05-31
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/159/05159667.pdf
[firstpage_image] =>[orig_patent_app_number] => 359839
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/359839 | Document identification by characteristics matching | May 30, 1989 | Issued |
Array
(
[id] => 2801833
[patent_doc_number] => 05136595
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-04
[patent_title] => 'Microprocessor operable in a functional redundancy monitor mode'
[patent_app_type] => 1
[patent_app_number] => 7/356291
[patent_app_country] => US
[patent_app_date] => 1989-05-24
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/356291 | Microprocessor operable in a functional redundancy monitor mode | May 23, 1989 | Issued |
07/356622 | HIGH PERFORMANCE MICROPROCESSOR | May 21, 1989 | Abandoned |
07/351997 | LARGE-SCALE DATA SYSTEM WITH ELECTRONIC TOKEN MODULES | May 14, 1989 | Abandoned |
Array
(
[id] => 3064735
[patent_doc_number] => 05307469
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-26
[patent_title] => 'Multiple mode memory module'
[patent_app_type] => 1
[patent_app_number] => 7/348318
[patent_app_country] => US
[patent_app_date] => 1989-05-05
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 6513
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[pdf_file] => patents/05/307/05307469.pdf
[firstpage_image] =>[orig_patent_app_number] => 348318
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/348318 | Multiple mode memory module | May 4, 1989 | Issued |
07/342714 | DESTINATION CONTROL LOGIC FOR ARITHMETIC AND LOGIC UNIT FOR DIGITAL DATA PROCESSOR | Apr 23, 1989 | Abandoned |
Array
(
[id] => 2775684
[patent_doc_number] => 05036454
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-30
[patent_title] => 'Horizontal computer having register multiconnect for execution of a loop with overlapped code'
[patent_app_type] => 1
[patent_app_number] => 7/342649
[patent_app_country] => US
[patent_app_date] => 1989-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 23803
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[pdf_file] => patents/05/036/05036454.pdf
[firstpage_image] =>[orig_patent_app_number] => 342649
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/342649 | Horizontal computer having register multiconnect for execution of a loop with overlapped code | Apr 23, 1989 | Issued |
07/340985 | PROCESS CONTROLLER SINGLE MEMORY CHIP SHADOWING TECHNIQUE | Apr 19, 1989 | Abandoned |
Array
(
[id] => 2799200
[patent_doc_number] => 05155823
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-13
[patent_title] => 'Address generating unit'
[patent_app_type] => 1
[patent_app_number] => 7/339111
[patent_app_country] => US
[patent_app_date] => 1989-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[pdf_file] => patents/05/155/05155823.pdf
[firstpage_image] =>[orig_patent_app_number] => 339111
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/339111 | Address generating unit | Apr 16, 1989 | Issued |
07/338552 | METHOD OF CONSTRUCTION OF HIERARCHICALLY ORGANIZED PROCEDURAL NODE INFORMATION STRUCTURE INCLUDING A METHOD FOR EXTRACTING PROCEDURAL KNOWLEDGE FROM AN EXPERT, AND PROCEDURAL NODE INFORMATION STRUCTURE CONSTRUCTED THEREBY | Apr 10, 1989 | Abandoned |
Array
(
[id] => 2676298
[patent_doc_number] => 05070451
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-03
[patent_title] => 'Forth specific language microprocessor'
[patent_app_type] => 1
[patent_app_number] => 7/336632
[patent_app_country] => US
[patent_app_date] => 1989-04-10
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[firstpage_image] =>[orig_patent_app_number] => 336632
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/336632 | Forth specific language microprocessor | Apr 9, 1989 | Issued |
Array
(
[id] => 2787609
[patent_doc_number] => 05151982
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-09-29
[patent_title] => 'Data processing system'
[patent_app_type] => 1
[patent_app_number] => 7/329210
[patent_app_country] => US
[patent_app_date] => 1989-03-27
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 329210
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/329210 | Data processing system | Mar 26, 1989 | Issued |
Array
(
[id] => 2939649
[patent_doc_number] => 05187783
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-02-16
[patent_title] => 'Controller for direct memory access'
[patent_app_type] => 1
[patent_app_number] => 7/324211
[patent_app_country] => US
[patent_app_date] => 1989-03-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/324211 | Controller for direct memory access | Mar 14, 1989 | Issued |
Array
(
[id] => 2822703
[patent_doc_number] => 05079693
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-01-07
[patent_title] => 'Bidirectional FIFO buffer having reread and rewrite means'
[patent_app_type] => 1
[patent_app_number] => 7/317204
[patent_app_country] => US
[patent_app_date] => 1989-02-28
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 317204
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/317204 | Bidirectional FIFO buffer having reread and rewrite means | Feb 27, 1989 | Issued |
07/314799 | MEMORY CONTROLLER HAVING MEANS FOR COMPARING A DESIGNATED ADDRESS WITH ADDRESSES SETTING AN AREA IN A MEMORY | Feb 23, 1989 | Abandoned |
Array
(
[id] => 2872389
[patent_doc_number] => 05167011
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-11-24
[patent_title] => 'Method for coodinating information storage and retrieval'
[patent_app_type] => 1
[patent_app_number] => 7/311230
[patent_app_country] => US
[patent_app_date] => 1989-02-15
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/167/05167011.pdf
[firstpage_image] =>[orig_patent_app_number] => 311230
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/311230 | Method for coodinating information storage and retrieval | Feb 14, 1989 | Issued |