Search

Phuong Chi Thi Nguyen

Examiner (ID: 7373)

Most Active Art Unit
2831
Art Unit(s)
2832, 2833, 2839, 2831, 2834
Total Applications
2578
Issued Applications
2322
Pending Applications
50
Abandoned Applications
233

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4549043 [patent_doc_number] => 07925837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-12 [patent_title] => 'Maintaining write cache and parity update footprint coherency in multiple storage adaptor configuration' [patent_app_type] => utility [patent_app_number] => 12/041807 [patent_app_country] => US [patent_app_date] => 2008-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4680 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/925/07925837.pdf [firstpage_image] =>[orig_patent_app_number] => 12041807 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/041807
Maintaining write cache and parity update footprint coherency in multiple storage adaptor configuration Mar 3, 2008 Issued
Array ( [id] => 5387411 [patent_doc_number] => 20090228656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-10 [patent_title] => 'Associativity Implementation in a System With Directly Attached Processor Memory' [patent_app_type] => utility [patent_app_number] => 12/041894 [patent_app_country] => US [patent_app_date] => 2008-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6954 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20090228656.pdf [firstpage_image] =>[orig_patent_app_number] => 12041894 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/041894
Associativity implementation in a system with directly attached processor memory Mar 3, 2008 Issued
Array ( [id] => 5537961 [patent_doc_number] => 20090219766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-03 [patent_title] => 'APPARATUS, SYSTEM, AND METHOD FOR ADJUSTING MEMORY HOLD TIME' [patent_app_type] => utility [patent_app_number] => 12/039586 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5957 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20090219766.pdf [firstpage_image] =>[orig_patent_app_number] => 12039586 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/039586
Apparatus, system, and method for adjusting memory hold time Feb 27, 2008 Issued
Array ( [id] => 5516647 [patent_doc_number] => 20090216954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'APPARATUS, SYSTEM, AND METHOD FOR SELECTING A SPACE EFFICIENT REPOSITORY' [patent_app_type] => utility [patent_app_number] => 12/038557 [patent_app_country] => US [patent_app_date] => 2008-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5981 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20090216954.pdf [firstpage_image] =>[orig_patent_app_number] => 12038557 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/038557
Apparatus, system, and method for selecting a space efficient repository Feb 26, 2008 Issued
Array ( [id] => 5266978 [patent_doc_number] => 20090119663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'IOMMU WITH TRANSLATION REQUEST MANAGEMENT AND METHODS FOR MANAGING TRANSLATION REQUESTS' [patent_app_type] => utility [patent_app_number] => 11/933790 [patent_app_country] => US [patent_app_date] => 2007-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4808 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20090119663.pdf [firstpage_image] =>[orig_patent_app_number] => 11933790 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/933790
Iommu with translation request management and methods for managing translation requests Oct 31, 2007 Issued
Array ( [id] => 5266786 [patent_doc_number] => 20090119471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'Priority-Based Memory Prefetcher' [patent_app_type] => utility [patent_app_number] => 11/933457 [patent_app_country] => US [patent_app_date] => 2007-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3198 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20090119471.pdf [firstpage_image] =>[orig_patent_app_number] => 11933457 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/933457
Priority-based memory prefetcher Oct 31, 2007 Issued
Array ( [id] => 5266759 [patent_doc_number] => 20090119444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'MULTIPLE WRITE CYCLE MEMORY USING REDUNDANT ADDRESSING' [patent_app_type] => utility [patent_app_number] => 11/933801 [patent_app_country] => US [patent_app_date] => 2007-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5574 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20090119444.pdf [firstpage_image] =>[orig_patent_app_number] => 11933801 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/933801
MULTIPLE WRITE CYCLE MEMORY USING REDUNDANT ADDRESSING Oct 31, 2007 Abandoned
Array ( [id] => 4585716 [patent_doc_number] => 07856533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-21 [patent_title] => 'Probabilistic method for performing memory prefetching' [patent_app_type] => utility [patent_app_number] => 11/933456 [patent_app_country] => US [patent_app_date] => 2007-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2866 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/856/07856533.pdf [firstpage_image] =>[orig_patent_app_number] => 11933456 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/933456
Probabilistic method for performing memory prefetching Oct 31, 2007 Issued
Array ( [id] => 4462315 [patent_doc_number] => 07895402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Method of accessing data in a deinterleaving device' [patent_app_type] => utility [patent_app_number] => 11/933246 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3404 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/895/07895402.pdf [firstpage_image] =>[orig_patent_app_number] => 11933246 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/933246
Method of accessing data in a deinterleaving device Oct 30, 2007 Issued
Array ( [id] => 8149262 [patent_doc_number] => 08166275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-24 [patent_title] => 'Method and apparatus for accessing a multi ordered memory array' [patent_app_type] => utility [patent_app_number] => 11/931833 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7612 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/166/08166275.pdf [firstpage_image] =>[orig_patent_app_number] => 11931833 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/931833
Method and apparatus for accessing a multi ordered memory array Oct 30, 2007 Issued
Array ( [id] => 107667 [patent_doc_number] => 07725662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Hardware acceleration for a software transactional memory system' [patent_app_type] => utility [patent_app_number] => 11/926440 [patent_app_country] => US [patent_app_date] => 2007-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8985 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/725/07725662.pdf [firstpage_image] =>[orig_patent_app_number] => 11926440 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/926440
Hardware acceleration for a software transactional memory system Oct 28, 2007 Issued
Array ( [id] => 4508077 [patent_doc_number] => 07958319 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Hardware acceleration for a software transactional memory system' [patent_app_type] => utility [patent_app_number] => 11/926423 [patent_app_country] => US [patent_app_date] => 2007-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8996 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/958/07958319.pdf [firstpage_image] =>[orig_patent_app_number] => 11926423 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/926423
Hardware acceleration for a software transactional memory system Oct 28, 2007 Issued
Array ( [id] => 4881799 [patent_doc_number] => 20080155182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'NON-VOLATILE SEMICONDUCTOR MEMORY SYSTEM AND DATA WRITE METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/923041 [patent_app_country] => US [patent_app_date] => 2007-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3584 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20080155182.pdf [firstpage_image] =>[orig_patent_app_number] => 11923041 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/923041
NON-VOLATILE SEMICONDUCTOR MEMORY SYSTEM AND DATA WRITE METHOD THEREOF Oct 23, 2007 Abandoned
Array ( [id] => 97230 [patent_doc_number] => 07739475 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-15 [patent_title] => 'System and method for updating dirty data of designated raw device' [patent_app_type] => utility [patent_app_number] => 11/923461 [patent_app_country] => US [patent_app_date] => 2007-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2992 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/739/07739475.pdf [firstpage_image] =>[orig_patent_app_number] => 11923461 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/923461
System and method for updating dirty data of designated raw device Oct 23, 2007 Issued
Array ( [id] => 5332655 [patent_doc_number] => 20090113132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'PREFERRED WRITE-MOSTLY DATA CACHE REPLACEMENT POLICIES' [patent_app_type] => utility [patent_app_number] => 11/923625 [patent_app_country] => US [patent_app_date] => 2007-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20090113132.pdf [firstpage_image] =>[orig_patent_app_number] => 11923625 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/923625
Preferred write-mostly data cache replacement policies Oct 23, 2007 Issued
Array ( [id] => 4917573 [patent_doc_number] => 20080098174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'CACHE MEMORY HAVING PIPELINE STRUCTURE AND METHOD FOR CONTROLLING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/877874 [patent_app_country] => US [patent_app_date] => 2007-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5972 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20080098174.pdf [firstpage_image] =>[orig_patent_app_number] => 11877874 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/877874
Cache memory having pipeline structure and method for controlling the same Oct 23, 2007 Issued
Array ( [id] => 5325768 [patent_doc_number] => 20090063758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'PROGRAM AND READ METHOD AND PROGRAM APPARATUS OF NAND FLASH MEMORY' [patent_app_type] => utility [patent_app_number] => 11/923647 [patent_app_country] => US [patent_app_date] => 2007-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7019 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20090063758.pdf [firstpage_image] =>[orig_patent_app_number] => 11923647 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/923647
PROGRAM AND READ METHOD AND PROGRAM APPARATUS OF NAND FLASH MEMORY Oct 23, 2007 Abandoned
Array ( [id] => 5424139 [patent_doc_number] => 20090150595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'BALANCED PROGRAMMING RATE FOR MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 11/877798 [patent_app_country] => US [patent_app_date] => 2007-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 13235 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20090150595.pdf [firstpage_image] =>[orig_patent_app_number] => 11877798 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/877798
BALANCED PROGRAMMING RATE FOR MEMORY CELLS Oct 23, 2007 Abandoned
Array ( [id] => 7510264 [patent_doc_number] => 08037240 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'System and method for using reversed backup operation for minimizing the disk spinning time and the number of spin-up operations' [patent_app_type] => utility [patent_app_number] => 11/877947 [patent_app_country] => US [patent_app_date] => 2007-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6652 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/037/08037240.pdf [firstpage_image] =>[orig_patent_app_number] => 11877947 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/877947
System and method for using reversed backup operation for minimizing the disk spinning time and the number of spin-up operations Oct 23, 2007 Issued
Array ( [id] => 4735497 [patent_doc_number] => 20080052479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Storage system, method of controlling storage system, and storage device' [patent_app_type] => utility [patent_app_number] => 11/907643 [patent_app_country] => US [patent_app_date] => 2007-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9036 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20080052479.pdf [firstpage_image] =>[orig_patent_app_number] => 11907643 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/907643
Storage system, method of controlling storage system, and storage device Oct 15, 2007 Abandoned
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