Phuong T. Bui

Array ( [id] => 4116563 [patent_doc_number] => 06067633 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Design and methodology for manufacturing data processing systems having multiple processors' [patent_app_type] => 1 [patent_app_number] => 9/052248 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4915 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/067/06067633.pdf [firstpage_image] =>[orig_patent_app_number] => 052248 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4279822 [patent_doc_number] => 06205520 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Method and apparatus for implementing non-temporal stores' [patent_app_type] => 1 [patent_app_number] => 9/053387 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7743 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205520.pdf [firstpage_image] =>[orig_patent_app_number] => 053387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4239267 [patent_doc_number] => 06088787 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Enhanced program counter stack for multi-tasking central processing unit' [patent_app_type] => 1 [patent_app_number] => 9/049918 [patent_app_country] => US [patent_app_date] => 1998-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2637 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088787.pdf [firstpage_image] =>[orig_patent_app_number] => 049918 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4152817 [patent_doc_number] => 06148391 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'System for simultaneously accessing one or more stack elements by multiple functional units using real stack addresses' [patent_app_type] => 1 [patent_app_number] => 9/049163 [patent_app_country] => US [patent_app_date] => 1998-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 19680 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148391.pdf [firstpage_image] =>[orig_patent_app_number] => 049163 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4199300 [patent_doc_number] => 06038657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Scan chains for out-of-order load/store execution control' [patent_app_type] => 1 [patent_app_number] => 9/040087 [patent_app_country] => US [patent_app_date] => 1998-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 15420 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038657.pdf [firstpage_image] =>[orig_patent_app_number] => 040087 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309941 [patent_doc_number] => 06212590 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Computer system having integrated bus bridge design with delayed transaction arbitration mechanism employed within laptop computer docked to expansion base' [patent_app_type] => 1 [patent_app_number] => 9/042038 [patent_app_country] => US [patent_app_date] => 1998-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 14831 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212590.pdf [firstpage_image] =>[orig_patent_app_number] => 042038 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4103899 [patent_doc_number] => 06026480 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Processor having bug avoidance function and method for avoiding bug in processor' [patent_app_type] => 1 [patent_app_number] => 9/037067 [patent_app_country] => US [patent_app_date] => 1998-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4406 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026480.pdf [firstpage_image] =>[orig_patent_app_number] => 037067 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4147713 [patent_doc_number] => 06128717 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Method and apparatus for storage application programming interface for digital mass storage and retrieval based upon data object type or size and characteristics of the data storage device' [patent_app_type] => 1 [patent_app_number] => 9/009622 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 9625 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128717.pdf [firstpage_image] =>[orig_patent_app_number] => 009622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4252613 [patent_doc_number] => 06076154 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'VLIW processor has different functional units operating on commands of different widths' [patent_app_type] => 1 [patent_app_number] => 9/008339 [patent_app_country] => US [patent_app_date] => 1998-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3883 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/076/06076154.pdf [firstpage_image] =>[orig_patent_app_number] => 008339 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1539255 [patent_doc_number] => 06412061 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Dynamic pipelines with reusable logic elements controlled by a set of multiplexers for pipeline stage selection' [patent_app_type] => B1 [patent_app_number] => 09/007029 [patent_app_country] => US [patent_app_date] => 1998-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9444 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/412/06412061.pdf [firstpage_image] =>[orig_patent_app_number] => 09007029 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4161523 [patent_doc_number] => 06032178 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Method and arrangement for data transmission between units on a bus system selectively transmitting data in one of a first and a second data transmission configurations' [patent_app_type] => 1 [patent_app_number] => 9/005696 [patent_app_country] => US [patent_app_date] => 1998-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6584 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/032/06032178.pdf [firstpage_image] =>[orig_patent_app_number] => 005696 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4152263 [patent_doc_number] => 06035408 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Portable computer with dual switchable processors for selectable power consumption' [patent_app_type] => 1 [patent_app_number] => 9/003284 [patent_app_country] => US [patent_app_date] => 1998-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1728 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035408.pdf [firstpage_image] =>[orig_patent_app_number] => 003284 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4204101 [patent_doc_number] => 06161198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'System for providing transaction indivisibility in a transaction processing system upon recovery from a host processor failure by monitoring source message sequencing' [patent_app_type] => 1 [patent_app_number] => 8/997322 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5685 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/161/06161198.pdf [firstpage_image] =>[orig_patent_app_number] => 997322 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4237520 [patent_doc_number] => 06112296 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Floating point stack manipulation using a register map and speculative top of stack values' [patent_app_type] => 1 [patent_app_number] => 8/992805 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 14917 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112296.pdf [firstpage_image] =>[orig_patent_app_number] => 992805 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4148888 [patent_doc_number] => 06016545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Reduced size storage apparatus for storing cache-line-related data in a high frequency microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/991694 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12054 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016545.pdf [firstpage_image] =>[orig_patent_app_number] => 991694 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4204115 [patent_doc_number] => 06161199 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Non-intrusive in-system debugging for a microcontroller with in-system programming capabilities using in-system debugging circuitry and program embedded in-system debugging commands' [patent_app_type] => 1 [patent_app_number] => 8/989830 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 5902 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/161/06161199.pdf [firstpage_image] =>[orig_patent_app_number] => 989830 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4272869 [patent_doc_number] => 06209022 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Slave station with two output circuits commonly and directly connected to a line for serially transmitting data to a master station in two operational modes' [patent_app_type] => 1 [patent_app_number] => 8/987886 [patent_app_country] => US [patent_app_date] => 1997-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6056 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/209/06209022.pdf [firstpage_image] =>[orig_patent_app_number] => 987886 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3971583 [patent_doc_number] => 06000044 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Apparatus for randomly sampling instructions in a processor pipeline' [patent_app_type] => 1 [patent_app_number] => 8/980190 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 15635 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000044.pdf [firstpage_image] =>[orig_patent_app_number] => 980190 [rel_patent_id] =>[rel_patent_doc_number] =>)