Search

Pierre E Elisca

Examiner (ID: 9174, Phone: (571)272-6706 , Office: P/3716 )

Most Active Art Unit
3715
Art Unit(s)
3718, 2785, 3714, 3716, 2131, 3621, 2161, 3715
Total Applications
2631
Issued Applications
2140
Pending Applications
221
Abandoned Applications
269

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17933499 [patent_doc_number] => 20220328625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => CONVERGENT FIN AND NANOSTRUCTURE TRANSISTOR STRUCTURE AND METHOD [patent_app_type] => utility [patent_app_number] => 17/480103 [patent_app_country] => US [patent_app_date] => 2021-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11983 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480103 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480103
CONVERGENT FIN AND NANOSTRUCTURE TRANSISTOR STRUCTURE AND METHOD Sep 19, 2021 Pending
Array ( [id] => 18256393 [patent_doc_number] => 20230083432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => BURIED POWER RAIL FOR SEMICONDUCTORS [patent_app_type] => utility [patent_app_number] => 17/474271 [patent_app_country] => US [patent_app_date] => 2021-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6461 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17474271 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/474271
BURIED POWER RAIL FOR SEMICONDUCTORS Sep 13, 2021 Pending
Array ( [id] => 19277356 [patent_doc_number] => 12027488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => Methods of forming stacked integrated circuits using selective thermal atomic layer deposition on conductive contacts and structures formed using the same [patent_app_type] => utility [patent_app_number] => 17/470630 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 4804 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470630 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470630
Methods of forming stacked integrated circuits using selective thermal atomic layer deposition on conductive contacts and structures formed using the same Sep 8, 2021 Issued
Array ( [id] => 19414900 [patent_doc_number] => 12080738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Image sensor having stacked metal oxide films as fixed charge film [patent_app_type] => utility [patent_app_number] => 17/400647 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17400647 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/400647
Image sensor having stacked metal oxide films as fixed charge film Aug 11, 2021 Issued
Array ( [id] => 17232237 [patent_doc_number] => 20210358794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH NAND LOGIC [patent_app_type] => utility [patent_app_number] => 17/384793 [patent_app_country] => US [patent_app_date] => 2021-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 79543 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17384793 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/384793
3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH NAND LOGIC Jul 24, 2021 Abandoned
Array ( [id] => 17203476 [patent_doc_number] => 20210343571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => METHODS FOR PRODUCING A 3D SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/377042 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 79628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377042 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/377042
Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors Jul 14, 2021 Issued
Array ( [id] => 18097214 [patent_doc_number] => 20220415555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => INDUCTOR AND TRANSFORMER SEMICONDUCTOR DEVICES USING HYBRID BONDING TECHNOLOGY [patent_app_type] => utility [patent_app_number] => 17/359165 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11070 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359165 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359165
INDUCTOR AND TRANSFORMER SEMICONDUCTOR DEVICES USING HYBRID BONDING TECHNOLOGY Jun 24, 2021 Pending
Array ( [id] => 17130327 [patent_doc_number] => 20210305096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => FAN-OUT WAFER LEVEL PACKAGING OF SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/304136 [patent_app_country] => US [patent_app_date] => 2021-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17304136 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/304136
FAN-OUT WAFER LEVEL PACKAGING OF SEMICONDUCTOR DEVICES Jun 14, 2021 Pending
Array ( [id] => 17373640 [patent_doc_number] => 20220028692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/344457 [patent_app_country] => US [patent_app_date] => 2021-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17344457 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/344457
Improving resolution of masks for semiconductor manufacture Jun 9, 2021 Issued
Array ( [id] => 17115645 [patent_doc_number] => 20210296242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => SIDE MOUNTED INTERCONNECT BRIDGES [patent_app_type] => utility [patent_app_number] => 17/340781 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7260 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340781 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340781
SIDE MOUNTED INTERCONNECT BRIDGES Jun 6, 2021 Pending
Array ( [id] => 17933378 [patent_doc_number] => 20220328504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => BIT CELL STRUCTURE FOR ONE-TIME-PROGRAMMING [patent_app_type] => utility [patent_app_number] => 17/320234 [patent_app_country] => US [patent_app_date] => 2021-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3043 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17320234 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/320234
BIT CELL STRUCTURE FOR ONE-TIME-PROGRAMMING May 13, 2021 Pending
Array ( [id] => 17056132 [patent_doc_number] => 20210265566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => CONFINING FILAMENT AT PILLAR CENTER FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/315996 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6753 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315996 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/315996
Confining filament at pillar center for memory devices May 9, 2021 Issued
Array ( [id] => 16920514 [patent_doc_number] => 20210193606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => SEMICONDUCTOR DEVICE ASSEMBLY WITH SURFACE-MOUNT DIE SUPPORT STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/198144 [patent_app_country] => US [patent_app_date] => 2021-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4649 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198144 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/198144
Semiconductor device assembly with surface-mount die support structures Mar 9, 2021 Issued
Array ( [id] => 16873563 [patent_doc_number] => 20210167030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => SEMICONDUCTOR DEVICE ASSEMBLY WITH DIE SUPPORT STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/174905 [patent_app_country] => US [patent_app_date] => 2021-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5772 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17174905 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/174905
SEMICONDUCTOR DEVICE ASSEMBLY WITH DIE SUPPORT STRUCTURES Feb 11, 2021 Pending
Array ( [id] => 17477474 [patent_doc_number] => 20220084978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => Integrated Half-Bridge Power Converter [patent_app_type] => utility [patent_app_number] => 17/169320 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13191 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17169320 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/169320
Integrated half-bridge power converter Feb 4, 2021 Issued
Array ( [id] => 19081094 [patent_doc_number] => 11950490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Display device having conductive spacers connecting anode and cathode on opposing substrates [patent_app_type] => utility [patent_app_number] => 17/169099 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5385 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17169099 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/169099
Display device having conductive spacers connecting anode and cathode on opposing substrates Feb 4, 2021 Issued
Array ( [id] => 17752484 [patent_doc_number] => 20220230689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => ARRAY OF ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY (EEPROM) AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/151226 [patent_app_country] => US [patent_app_date] => 2021-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2358 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17151226 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/151226
ARRAY OF ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY (EEPROM) AND FORMING METHOD THEREOF Jan 17, 2021 Pending
Array ( [id] => 16796085 [patent_doc_number] => 20210125902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => SEMICONDUCTOR DEVICE WITH METAL DIE ATTACH TO SUBSTRATE WITH MULTI-SIZE CAVITY [patent_app_type] => utility [patent_app_number] => 17/142598 [patent_app_country] => US [patent_app_date] => 2021-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3102 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17142598 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/142598
Semiconductor device with metal die attach to substrate with multi-size cavity Jan 5, 2021 Issued
Array ( [id] => 17403211 [patent_doc_number] => 20220045302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => DISPLAY DEVICE AND ORGANIC LIGHT-EMITTING DIODE PANEL THEREOF, AND METHOD FOR MANUFACTURING ORGANIC LIGHT-EMITTING DIODE PANEL [patent_app_type] => utility [patent_app_number] => 17/416497 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7350 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17416497 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/416497
DISPLAY DEVICE AND ORGANIC LIGHT-EMITTING DIODE PANEL THEREOF, AND METHOD FOR MANUFACTURING ORGANIC LIGHT-EMITTING DIODE PANEL Nov 24, 2020 Pending
Array ( [id] => 16731117 [patent_doc_number] => 20210098265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => METHOD FOR MODIFYING THE STRAIN STATE OF A BLOCK OF A SEMICONDUCTING MATERIAL [patent_app_type] => utility [patent_app_number] => 17/103219 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2904 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103219 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103219
METHOD FOR MODIFYING THE STRAIN STATE OF A BLOCK OF A SEMICONDUCTING MATERIAL Nov 23, 2020 Pending
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