Search

Pierre E Elisca

Examiner (ID: 9174, Phone: (571)272-6706 , Office: P/3716 )

Most Active Art Unit
3715
Art Unit(s)
3718, 2785, 3714, 3716, 2131, 3621, 2161, 3715
Total Applications
2631
Issued Applications
2140
Pending Applications
221
Abandoned Applications
269

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8171651 [patent_doc_number] => 20120107576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'TAPE FOR HOLDING CHIP, METHOD OF HOLDING CHIP-SHAPED WORKPIECE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING TAPE FOR HOLDING CHIP, AND METHOD OF MANUFACTURING TAPE FOR HOLDING CHIP' [patent_app_type] => utility [patent_app_number] => 13/347432 [patent_app_country] => US [patent_app_date] => 2012-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 20885 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20120107576.pdf [firstpage_image] =>[orig_patent_app_number] => 13347432 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/347432
TAPE FOR HOLDING CHIP, METHOD OF HOLDING CHIP-SHAPED WORKPIECE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING TAPE FOR HOLDING CHIP, AND METHOD OF MANUFACTURING TAPE FOR HOLDING CHIP Jan 9, 2012 Abandoned
Array ( [id] => 8154592 [patent_doc_number] => 20120097964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'Semiconductor Device and Manufacturing Method Thereof' [patent_app_type] => utility [patent_app_number] => 13/343474 [patent_app_country] => US [patent_app_date] => 2012-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 15781 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20120097964.pdf [firstpage_image] =>[orig_patent_app_number] => 13343474 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/343474
Semiconductor device including first and second or drain electrodes and manufacturing method thereof Jan 3, 2012 Issued
Array ( [id] => 9446390 [patent_doc_number] => 20140117558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'SELF-ENCLOSED ASYMMETRIC INTERCONNECT STRUCTURES' [patent_app_type] => utility [patent_app_number] => 13/976456 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10743 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976456 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/976456
Self-enclosed asymmetric interconnect structures Dec 29, 2011 Issued
Array ( [id] => 9662185 [patent_doc_number] => 08809160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Methods for forming high-K crystalline films and related devices' [patent_app_type] => utility [patent_app_number] => 13/334618 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 13011 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13334618 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/334618
Methods for forming high-K crystalline films and related devices Dec 21, 2011 Issued
Array ( [id] => 11466846 [patent_doc_number] => 09583487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'Semiconductor device having metallic source and drain regions' [patent_app_type] => utility [patent_app_number] => 13/995419 [patent_app_country] => US [patent_app_date] => 2011-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 7743 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13995419 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/995419
Semiconductor device having metallic source and drain regions Dec 18, 2011 Issued
Array ( [id] => 9255219 [patent_doc_number] => 08618638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-31 [patent_title] => 'Semiconductor optical modulator and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/311837 [patent_app_country] => US [patent_app_date] => 2011-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 5267 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13311837 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/311837
Semiconductor optical modulator and method for manufacturing the same Dec 5, 2011 Issued
Array ( [id] => 9104637 [patent_doc_number] => 20130277768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'Semiconductor Structure And Method For Manufacturing The Same' [patent_app_type] => utility [patent_app_number] => 13/816228 [patent_app_country] => US [patent_app_date] => 2011-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4191 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13816228 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/816228
Semiconductor Structure And Method For Manufacturing The Same Nov 30, 2011 Abandoned
Array ( [id] => 9951713 [patent_doc_number] => 09000506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-07 [patent_title] => 'Variable resistance nonvolatile memory element and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/501624 [patent_app_country] => US [patent_app_date] => 2011-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 15222 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13501624 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/501624
Variable resistance nonvolatile memory element and method for manufacturing the same Nov 17, 2011 Issued
Array ( [id] => 9889461 [patent_doc_number] => 08975721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-10 [patent_title] => 'Integrated circuit having an edge passivation and oxidation resistant layer and method' [patent_app_type] => utility [patent_app_number] => 13/291664 [patent_app_country] => US [patent_app_date] => 2011-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10668 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13291664 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/291664
Integrated circuit having an edge passivation and oxidation resistant layer and method Nov 7, 2011 Issued
Array ( [id] => 8090131 [patent_doc_number] => 20120080676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => 'Backside nanoscale texturing to improve IR response of silicon solar cells and photodetectors' [patent_app_type] => utility [patent_app_number] => 13/373074 [patent_app_country] => US [patent_app_date] => 2011-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6177 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20120080676.pdf [firstpage_image] =>[orig_patent_app_number] => 13373074 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/373074
Backside nanoscale texturing to improve IR response of silicon solar cells and photodetectors Nov 2, 2011 Abandoned
Array ( [id] => 7773187 [patent_doc_number] => 20120038043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'MANUFACTURING FAN-OUT WAFER LEVEL PACKAGING' [patent_app_type] => utility [patent_app_number] => 13/280186 [patent_app_country] => US [patent_app_date] => 2011-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6472 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20120038043.pdf [firstpage_image] =>[orig_patent_app_number] => 13280186 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/280186
MANUFACTURING FAN-OUT WAFER LEVEL PACKAGING Oct 23, 2011 Abandoned
Array ( [id] => 7818103 [patent_doc_number] => 20120064723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING DUAL DAMASCENE PROCESS' [patent_app_type] => utility [patent_app_number] => 13/278997 [patent_app_country] => US [patent_app_date] => 2011-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2604 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20120064723.pdf [firstpage_image] =>[orig_patent_app_number] => 13278997 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/278997
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING DUAL DAMASCENE PROCESS Oct 20, 2011 Abandoned
Array ( [id] => 7767272 [patent_doc_number] => 20120034773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-09 [patent_title] => 'TRANSISTOR HAVING AN ETCH STOP LAYER INCLUDING A METAL COMPOUND THAT IS SELECTIVELY FORMED OVER A METAL GATE, AND METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 13/273771 [patent_app_country] => US [patent_app_date] => 2011-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9302 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20120034773.pdf [firstpage_image] =>[orig_patent_app_number] => 13273771 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/273771
Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate, and method therefor Oct 13, 2011 Issued
Array ( [id] => 8210357 [patent_doc_number] => 20120129301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/273712 [patent_app_country] => US [patent_app_date] => 2011-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 718 [patent_figures_cnt] => 718 [patent_no_of_words] => 191522 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13273712 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/273712
Method of constructing a semiconductor device and structure Oct 13, 2011 Issued
Array ( [id] => 8450794 [patent_doc_number] => 20120261740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'FLASH MEMORY AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/389720 [patent_app_country] => US [patent_app_date] => 2011-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1963 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13389720 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/389720
FLASH MEMORY AND METHOD FOR FABRICATING THE SAME Oct 13, 2011 Abandoned
Array ( [id] => 10590530 [patent_doc_number] => 09312150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Semiconductor device and method of forming a metallurgical interconnection between a chip and a substrate in a flip chip package' [patent_app_type] => utility [patent_app_number] => 13/268048 [patent_app_country] => US [patent_app_date] => 2011-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1985 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13268048 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/268048
Semiconductor device and method of forming a metallurgical interconnection between a chip and a substrate in a flip chip package Oct 6, 2011 Issued
Array ( [id] => 10590530 [patent_doc_number] => 09312150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Semiconductor device and method of forming a metallurgical interconnection between a chip and a substrate in a flip chip package' [patent_app_type] => utility [patent_app_number] => 13/268048 [patent_app_country] => US [patent_app_date] => 2011-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1985 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13268048 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/268048
Semiconductor device and method of forming a metallurgical interconnection between a chip and a substrate in a flip chip package Oct 6, 2011 Issued
Array ( [id] => 7728368 [patent_doc_number] => 20120013005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-19 [patent_title] => 'Packaging Structure and Method' [patent_app_type] => utility [patent_app_number] => 13/245181 [patent_app_country] => US [patent_app_date] => 2011-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2017 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20120013005.pdf [firstpage_image] =>[orig_patent_app_number] => 13245181 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/245181
Packaging Structure and Method Sep 25, 2011 Abandoned
Array ( [id] => 7728368 [patent_doc_number] => 20120013005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-19 [patent_title] => 'Packaging Structure and Method' [patent_app_type] => utility [patent_app_number] => 13/245181 [patent_app_country] => US [patent_app_date] => 2011-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2017 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20120013005.pdf [firstpage_image] =>[orig_patent_app_number] => 13245181 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/245181
Packaging Structure and Method Sep 25, 2011 Abandoned
Array ( [id] => 7728376 [patent_doc_number] => 20120013010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-19 [patent_title] => 'BONDING PAD FOR ANTI-PEELING PROPERTY AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/240960 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2898 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20120013010.pdf [firstpage_image] =>[orig_patent_app_number] => 13240960 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/240960
BONDING PAD FOR ANTI-PEELING PROPERTY AND METHOD FOR FABRICATING THE SAME Sep 21, 2011 Abandoned
Menu